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authorGabor Juhos <juhosg@openwrt.org>2010-12-08 10:15:04 +0000
committerGabor Juhos <juhosg@openwrt.org>2010-12-08 10:15:04 +0000
commit56474016557d5d492b5d259c183cb5e6edc51db9 (patch)
tree6cf4715a3e33e4e928b88bf8325a307565118eed /target/linux
parent418e052c05c9de090fde782ab320e2ca25a16761 (diff)
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ramips: ramips_esw: don't touch GPIO_PURPOSE register
It must have been set by the board initialization code. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24332 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ramips/files/drivers/net/ramips_esw.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c
index 87479c6544..23f9e481db 100644
--- a/target/linux/ramips/files/drivers/net/ramips_esw.c
+++ b/target/linux/ramips/files/drivers/net/ramips_esw.c
@@ -3,8 +3,6 @@
#include <rt305x_regs.h>
#include <rt305x_esw_platform.h>
-#define GPIO_PRUPOSE 0x60
-#define GPIO_MDIO_BIT (1<<7)
#define RT305X_ESW_PHY_WRITE (1 << 13)
#define RT305X_ESW_PHY_TOUT (5 * HZ)
#define RT305X_ESW_PHY_CONTROL_0 0xC0
@@ -27,17 +25,6 @@ ramips_esw_rr(struct rt305x_esw *esw, unsigned reg)
return __raw_readl(esw->base + reg);
}
-static void
-ramips_enable_mdio(int s)
-{
- u32 gpio = rt305x_sysc_rr(GPIO_PRUPOSE);
- if(s)
- gpio &= ~GPIO_MDIO_BIT;
- else
- gpio |= GPIO_MDIO_BIT;
- rt305x_sysc_wr(gpio, GPIO_PRUPOSE);
-}
-
u32
mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
u32 write_data)
@@ -45,7 +32,6 @@ mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
unsigned long volatile t_start = jiffies;
int ret = 0;
- ramips_enable_mdio(1);
while(1)
{
if(!(ramips_esw_rr(esw, RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)))
@@ -70,7 +56,6 @@ mii_mgr_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
}
}
out:
- ramips_enable_mdio(0);
if(ret)
printk(KERN_ERR "ramips_eth: MDIO timeout\n");
return ret;
@@ -111,11 +96,6 @@ rt305x_esw_hw_init(struct rt305x_esw *esw)
mii_mgr_write(esw, 0, 14, 0x65); //longer TP_IDL tail length
mii_mgr_write(esw, 0, 31, 0x8000); //select local register
- /* Port 5 Disabled */
- rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50)
- rt305x_sysc_wr(0xfff, 0x674); //GPIO41-GPIO50 output mode
- rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low
-
/* set default vlan */
ramips_esw_wr(esw, 0x2001, 0x50);
ramips_esw_wr(esw, 0x504f, 0x70);