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authorFelix Fietkau <nbd@openwrt.org>2014-06-10 09:06:25 +0000
committerFelix Fietkau <nbd@openwrt.org>2014-06-10 09:06:25 +0000
commit08bd449e86479b6d2de5a00dc9314047f022d80e (patch)
tree5391988b630b74270277dfda911ab8c4b6a301e6 /target/linux
parent37006f3b3756c398114c8081bc6187dd494e84a6 (diff)
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atheros: fix too short msleep
Use msleep(20) instead of msleep(10) to make code closer to reality since msleep can sleep for up to 20ms even we request shorter delay. All updated calls are located in PCI initialization routine which is called only once upon device boot. So there should be no performance issues caused by more longer delay. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41096 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/atheros/patches-3.10/105-ar2315_pci.patch4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/atheros/patches-3.10/105-ar2315_pci.patch b/target/linux/atheros/patches-3.10/105-ar2315_pci.patch
index 7a9714f3fa..7108d6c75f 100644
--- a/target/linux/atheros/patches-3.10/105-ar2315_pci.patch
+++ b/target/linux/atheros/patches-3.10/105-ar2315_pci.patch
@@ -198,11 +198,11 @@
+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/
+
+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
-+ msleep(10);
++ msleep(20);
+
+ reg &= ~AR2315_RESET_PCIDMA;
+ ar231x_write_reg(AR2315_RESET, reg);
-+ msleep(10);
++ msleep(20);
+
+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);