openwrt/upstream - upstream openwrt

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author	Felix Fietkau <nbd@openwrt.org>	2013-07-14 12:56:58 +0000
committer	Felix Fietkau <nbd@openwrt.org>	2013-07-14 12:56:58 +0000
commit	b95bdc8ab56e6aa53ed62d8766610f5975f05acd (patch)
tree	35e501ae6a2add0fb22f7bbc4bc7b400a57ea7d8 /target/linux/x86/base-files/lib
parent	e800436de35501dca50f1f086594197a55596c16 (diff)
download	upstream-b95bdc8ab56e6aa53ed62d8766610f5975f05acd.tar.gz upstream-b95bdc8ab56e6aa53ed62d8766610f5975f05acd.tar.bz2 upstream-b95bdc8ab56e6aa53ed62d8766610f5975f05acd.zip

kernel/base-files: clean up old code related to refreshing mtd partitions, it is no longer used anywhere

Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 37282

Diffstat (limited to 'target/linux/x86/base-files/lib')

-rw-r--r--

target/linux/x86/base-files/lib/upgrade/platform.sh

1 files changed, 0 insertions, 6 deletions

/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ // [[CITE]] Power-Modulus Algorithm // Schneier, Bruce (1996). Applied Cryptography: Protocols, Algorithms, and Source Code in C, // Second Edition (2nd ed.). Wiley. ISBN 978-0-471-11709-4, page 244 #include "kernel/yosys.h" #include "libs/bigint/BigIntegerLibrary.hh" YOSYS_NAMESPACE_BEGIN static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) { RTLIL::State padding = RTLIL::State::S0; if (arg.bits.size() > 0 && is_signed) padding = arg.bits.back(); while (int(arg.bits.size()) < width) arg.bits.push_back(padding); arg.bits.resize(width); } static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) { BigUnsigned mag; BigInteger::Sign sign = BigInteger::positive; State inv_sign_bit = RTLIL::State::S1; size_t num_bits = val.bits.size(); if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) { inv_sign_bit = RTLIL::State::S0; sign = BigInteger::negative; num_bits--; } for (size_t i = 0; i < num_bits; i++) if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1) mag.setBit(i, val.bits[i] == inv_sign_bit); else if (undef_bit_pos < 0) undef_bit_pos = i; if (sign == BigInteger::negative) mag += 1; return BigInteger(mag, sign); } static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos) { if (undef_bit_pos >= 0) return RTLIL::Const(RTLIL::State::Sx, result_len); BigUnsigned mag = val.getMagnitude(); RTLIL::Const result(0, result_len); if (!mag.isZero()) { if (val.getSign() < 0) { mag--; for (int i = 0; i < result_len; i++) result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; } else { for (int i = 0; i < result_len; i++) result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; } } #if 0 if (undef_bit_pos >= 0) for (int i = undef_bit_pos; i < result_len; i++) result.bits[i] = RTLIL::State::Sx; #endif return result; } static RTLIL::State logic_and(RTLIL::State a, RTLIL::State b) { if (a == RTLIL::State::S0) return RTLIL::State::S0; if (b == RTLIL::State::S0) return RTLIL::State::S0; if (a != RTLIL::State::S1) return RTLIL::State::Sx; if (b != RTLIL::State::S1) return RTLIL::State::Sx; return RTLIL::State::S1; } static RTLIL::State logic_or(RTLIL::State a, RTLIL::State b) { if (a == RTLIL::State::S1) return RTLIL::State::S1; if (b == RTLIL::State::S1) return RTLIL::State::S1; if (a != RTLIL::State::S0) return RTLIL::State::Sx; if (b != RTLIL::State::S0) return RTLIL::State::Sx; return RTLIL::State::S0; } static RTLIL::State logic_xor(RTLIL::State a, RTLIL::State b) { if (a != RTLIL::State::S0 && a != RTLIL::State::S1) return RTLIL::State::Sx; if (b != RTLIL::State::S0 && b != RTLIL::State::S1) return RTLIL::State::Sx; return a != b ? RTLIL::State::S1 : RTLIL::State::S0; } static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b) { if (a != RTLIL::State::S0 && a != RTLIL::State::S1) return RTLIL::State::Sx; if (b != RTLIL::State::S0 && b != RTLIL::State::S1) return RTLIL::State::Sx; return a == b ? RTLIL::State::S1 : RTLIL::State::S0; } RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { if (result_len < 0) result_len = arg1.bits.size(); RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, result_len, signed1); RTLIL::Const result(RTLIL::State::Sx, result_len); for (size_t i = 0; i < size_t(result_len); i++) { if (i >= arg1_ext.bits.size()) result.bits[i] = RTLIL::State::S0; else if (arg1_ext.bits[i] == RTLIL::State::S0) result.bits[i] = RTLIL::State::S1; else if (arg1_ext.bits[i] == RTLIL::State::S1) result.bits[i] = RTLIL::State::S0; } return result; } static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1) { if (result_len < 0) result_len = max(arg1.bits.size(), arg2.bits.size()); extend_u0(arg1, result_len, signed1); extend_u0(arg2, result_len, signed2); RTLIL::Const result(RTLIL::State::Sx, result_len); for (size_t i = 0; i < size_t(result_len); i++) { RTLIL::State a = i < arg1.bits.size() ? arg1.bits[i] : RTLIL::State::S0; RTLIL::State b = i < arg2.bits.size() ? arg2.bits[i] : RTLIL::State::S0; result.bits[i] = logic_func(a, b); } return result; } RTLIL::Const RTLIL::const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { return logic_wrapper(logic_and, arg1, arg2, signed1, signed2, result_len); } RTLIL::Const RTLIL::const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { return logic_wrapper(logic_or, arg1, arg2, signed1, signed2, result_len); } RTLIL::Const RTLIL::const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { return logic_wrapper(logic_xor, arg1, arg2, signed1, signed2, result_len); } RTLIL::Const RTLIL::const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)


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