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| author | Arturas Moskvinas <arturas.moskvinas@gmail.com> | 2020-08-11 23:03:53 +0300 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2020-10-11 18:29:26 +0200 |
| commit | 679db02b10474e8a685baeecc37ddd511f1d4808 (patch) | |
| tree | c7a0602059950aee8bb4dfe927cf0d59f2ce9ef1 /target/linux/sunxi | |
| parent | 37e62ec4ec811cb6d2c8c0b25202ad551e035413 (diff) | |
| download | upstream-679db02b10474e8a685baeecc37ddd511f1d4808.tar.gz upstream-679db02b10474e8a685baeecc37ddd511f1d4808.tar.bz2 upstream-679db02b10474e8a685baeecc37ddd511f1d4808.zip | |
sunxi: add support for FriendlyArm Zeropi
Specification
CPU: Allwinner H3, Quad-core Cortex-A7 Up to 1.2GHz
DDR3 RAM: 256MB/512MB
Connectivity: 10/100/1000Mbps Ethernet
USB Host: Type-A x 1
MicroSD Slot x 1
MicroUSB: for power input only
Debug Serial Port: 4Pin, 2.54 mm pitch pin header
Power Supply: DC 5V/2A
PCB Dimension: 40 x 40 x 1.2mm
Installation:
Burn the image file to an SD Card with dd or any image burning tool
Boot ZeroPi from the SD Card
The following features are working and tested:
Ethernet port 10/100/1000M Ethernet
Remarks: SBC is mostly compatible and boots with FriendlyARM NanoPI M1 plus DTS also (zeropi has no working hdmi)
Signed-off-by: Arturas Moskvinas <arturas.moskvinas@gmail.com>
Diffstat (limited to 'target/linux/sunxi')
| -rw-r--r-- | target/linux/sunxi/image/cortexa7.mk | 8 | ||||
| -rw-r--r-- | target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch | 79 |
2 files changed, 87 insertions, 0 deletions
diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk index 083010ad8c..a48aa2e03c 100644 --- a/target/linux/sunxi/image/cortexa7.mk +++ b/target/linux/sunxi/image/cortexa7.mk @@ -47,6 +47,14 @@ define Device/friendlyarm_nanopi-neo-air endef TARGET_DEVICES += friendlyarm_nanopi-neo-air +define Device/friendlyarm_zeropi + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := ZeroPi + DEVICE_PACKAGES := kmod-rtc-sunxi + SOC := sun8i-h3 +endef +TARGET_DEVICES += friendlyarm_zeropi + define Device/lamobo_lamobo-r1 DEVICE_VENDOR := Lamobo DEVICE_MODEL := Lamobo R1 diff --git a/target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch b/target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch new file mode 100644 index 0000000000..dc69f70bbe --- /dev/null +++ b/target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch @@ -0,0 +1,79 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1118,6 +1118,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ ++ sun8i-h3-zeropi.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts +@@ -0,0 +1,66 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "sun8i-h3-nanopi.dtsi" ++ ++/ { ++ model = "FriendlyElec ZeroPi"; ++ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; ++ ++ aliases { ++ ethernet0 = &emac; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac_power_pin_nanopi>; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <100000>; ++ enable-active-high; ++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&pio { ++ gmac_power_pin_nanopi: gmac_power_pin@0 { ++ pins = "PD6"; ++ function = "gpio_out"; ++ }; ++}; ++ ++&external_mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <7>; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-supply = <®_gmac_3v3>; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-mode = "rgmii"; ++ ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ status = "okay"; ++ dr_mode = "peripheral"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ ++}; |