kernel: delete Linux 5.4 config and patches

As the upcoming release will be based on Linux 5.10 only, remove all
kernel configuration as well as patches for Linux 5.4.
There were no targets still actively using Linux 5.4.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

1 files changed, 0 insertions, 305 deletions

diff --git a/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch b/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch
deleted file mode 100644
index eb254ee74d..0000000000
--- a/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch
+++ /dev/null
@@ -1,305 +0,0 @@
---- a/drivers/pwm/pwm-sun4i.c
-+++ b/drivers/pwm/pwm-sun4i.c
-@@ -3,6 +3,10 @@
-  * Driver for Allwinner sun4i Pulse Width Modulation Controller
-  *
-  * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
-+ *
-+ * Limitations:
-+ * - When outputing the source clock directly, the PWM logic will be bypassed
-+ *   and the currently running period is not guaranteed to be completed
-  */
- 
- #include <linux/bitops.h>
-@@ -16,6 +20,7 @@
- #include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/pwm.h>
-+#include <linux/reset.h>
- #include <linux/slab.h>
- #include <linux/spinlock.h>
- #include <linux/time.h>
-@@ -72,12 +77,15 @@ static const u32 prescaler_table[] = {
- 
- struct sun4i_pwm_data {
- 	bool has_prescaler_bypass;
-+	bool has_direct_mod_clk_output;
- 	unsigned int npwm;
- };
- 
- struct sun4i_pwm_chip {
- 	struct pwm_chip chip;
-+	struct clk *bus_clk;
- 	struct clk *clk;
-+	struct reset_control *rst;
- 	void __iomem *base;
- 	spinlock_t ctrl_lock;
- 	const struct sun4i_pwm_data *data;
-@@ -115,6 +123,20 @@ static void sun4i_pwm_get_state(struct p
- 
- 	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
- 
-+	/*
-+	 * PWM chapter in H6 manual has a diagram which explains that if bypass
-+	 * bit is set, no other setting has any meaning. Even more, experiment
-+	 * proved that also enable bit is ignored in this case.
-+	 */
-+	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
-+	    sun4i_pwm->data->has_direct_mod_clk_output) {
-+		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
-+		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
-+		state->polarity = PWM_POLARITY_NORMAL;
-+		state->enabled = true;
-+		return;
-+	}
-+
- 	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
- 	    sun4i_pwm->data->has_prescaler_bypass)
- 		prescaler = 1;
-@@ -146,13 +168,24 @@ static void sun4i_pwm_get_state(struct p
- 
- static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
- 			       const struct pwm_state *state,
--			       u32 *dty, u32 *prd, unsigned int *prsclr)
-+			       u32 *dty, u32 *prd, unsigned int *prsclr,
-+			       bool *bypass)
- {
- 	u64 clk_rate, div = 0;
- 	unsigned int pval, prescaler = 0;
- 
- 	clk_rate = clk_get_rate(sun4i_pwm->clk);
- 
-+	*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
-+		  state->enabled &&
-+		  (state->period * clk_rate >= NSEC_PER_SEC) &&
-+		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
-+		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
-+
-+	/* Skip calculation of other parameters if we bypass them */
-+	if (*bypass)
-+		return 0;
-+
- 	if (sun4i_pwm->data->has_prescaler_bypass) {
- 		/* First, test without any prescaler when available */
- 		prescaler = PWM_PRESCAL_MASK;
-@@ -200,10 +233,11 @@ static int sun4i_pwm_apply(struct pwm_ch
- {
- 	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
- 	struct pwm_state cstate;
--	u32 ctrl;
-+	u32 ctrl, duty, period, val;
- 	int ret;
--	unsigned int delay_us;
-+	unsigned int delay_us, prescaler;
- 	unsigned long now;
-+	bool bypass;
- 
- 	pwm_get_state(pwm, &cstate);
- 
-@@ -218,43 +252,50 @@ static int sun4i_pwm_apply(struct pwm_ch
- 	spin_lock(&sun4i_pwm->ctrl_lock);
- 	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
- 
--	if ((cstate.period != state->period) ||
--	    (cstate.duty_cycle != state->duty_cycle)) {
--		u32 period, duty, val;
--		unsigned int prescaler;
-+	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
-+				  &bypass);
-+	if (ret) {
-+		dev_err(chip->dev, "period exceeds the maximum value\n");
-+		spin_unlock(&sun4i_pwm->ctrl_lock);
-+		if (!cstate.enabled)
-+			clk_disable_unprepare(sun4i_pwm->clk);
-+		return ret;
-+	}
- 
--		ret = sun4i_pwm_calculate(sun4i_pwm, state,
--					  &duty, &period, &prescaler);
--		if (ret) {
--			dev_err(chip->dev, "period exceeds the maximum value\n");
-+	if (sun4i_pwm->data->has_direct_mod_clk_output) {
-+		if (bypass) {
-+			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
-+			/* We can skip other parameter */
-+			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
- 			spin_unlock(&sun4i_pwm->ctrl_lock);
--			if (!cstate.enabled)
--				clk_disable_unprepare(sun4i_pwm->clk);
--			return ret;
-+			return 0;
-+		} else {
-+			ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
- 		}
-+	}
- 
--		if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
--			/* Prescaler changed, the clock has to be gated */
--			ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
--			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
--
--			ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
--			ctrl |= BIT_CH(prescaler, pwm->hwpwm);
--		}
-+	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
-+		/* Prescaler changed, the clock has to be gated */
-+		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+		sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
- 
--		val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
--		sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
--		sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
--			usecs_to_jiffies(cstate.period / 1000 + 1);
--		sun4i_pwm->needs_delay[pwm->hwpwm] = true;
-+		ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
-+		ctrl |= BIT_CH(prescaler, pwm->hwpwm);
- 	}
- 
-+	val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
-+	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
-+	sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
-+		usecs_to_jiffies(cstate.period / 1000 + 1);
-+	sun4i_pwm->needs_delay[pwm->hwpwm] = true;
-+
- 	if (state->polarity != PWM_POLARITY_NORMAL)
- 		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
- 	else
- 		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
- 
- 	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+
- 	if (state->enabled) {
- 		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
- 	} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
-@@ -320,6 +361,12 @@ static const struct sun4i_pwm_data sun4i
- 	.npwm = 1,
- };
- 
-+static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
-+	.has_prescaler_bypass = true,
-+	.has_direct_mod_clk_output = true,
-+	.npwm = 2,
-+};
-+
- static const struct of_device_id sun4i_pwm_dt_ids[] = {
- 	{
- 		.compatible = "allwinner,sun4i-a10-pwm",
-@@ -337,6 +384,9 @@ static const struct of_device_id sun4i_p
- 		.compatible = "allwinner,sun8i-h3-pwm",
- 		.data = &sun4i_pwm_single_bypass,
- 	}, {
-+		.compatible = "allwinner,sun50i-h6-pwm",
-+		.data = &sun50i_h6_pwm_data,
-+	}, {
- 		/* sentinel */
- 	},
- };
-@@ -361,9 +411,69 @@ static int sun4i_pwm_probe(struct platfo
- 	if (IS_ERR(pwm->base))
- 		return PTR_ERR(pwm->base);
- 
--	pwm->clk = devm_clk_get(&pdev->dev, NULL);
--	if (IS_ERR(pwm->clk))
-+	/*
-+	 * All hardware variants need a source clock that is divided and
-+	 * then feeds the counter that defines the output wave form. In the
-+	 * device tree this clock is either unnamed or called "mod".
-+	 * Some variants (e.g. H6) need another clock to access the
-+	 * hardware registers; this is called "bus".
-+	 * So we request "mod" first (and ignore the corner case that a
-+	 * parent provides a "mod" clock while the right one would be the
-+	 * unnamed one of the PWM device) and if this is not found we fall
-+	 * back to the first clock of the PWM.
-+	 */
-+	pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
-+	if (IS_ERR(pwm->clk)) {
-+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "get mod clock failed %pe\n",
-+				pwm->clk);
- 		return PTR_ERR(pwm->clk);
-+	}
-+
-+	if (!pwm->clk) {
-+		pwm->clk = devm_clk_get(&pdev->dev, NULL);
-+		if (IS_ERR(pwm->clk)) {
-+			if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
-+				dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
-+					pwm->clk);
-+			return PTR_ERR(pwm->clk);
-+		}
-+	}
-+
-+	pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
-+	if (IS_ERR(pwm->bus_clk)) {
-+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "get bus clock failed %pe\n",
-+				pwm->bus_clk);
-+		return PTR_ERR(pwm->bus_clk);
-+	}
-+
-+	pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
-+	if (IS_ERR(pwm->rst)) {
-+		if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "get reset failed %pe\n",
-+				pwm->rst);
-+		return PTR_ERR(pwm->rst);
-+	}
-+
-+	/* Deassert reset */
-+	ret = reset_control_deassert(pwm->rst);
-+	if (ret) {
-+		dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
-+			ERR_PTR(ret));
-+		return ret;
-+	}
-+
-+	/*
-+	 * We're keeping the bus clock on for the sake of simplicity.
-+	 * Actually it only needs to be on for hardware register accesses.
-+	 */
-+	ret = clk_prepare_enable(pwm->bus_clk);
-+	if (ret) {
-+		dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
-+			ERR_PTR(ret));
-+		goto err_bus;
-+	}
- 
- 	pwm->chip.dev = &pdev->dev;
- 	pwm->chip.ops = &sun4i_pwm_ops;
-@@ -377,19 +487,34 @@ static int sun4i_pwm_probe(struct platfo
- 	ret = pwmchip_add(&pwm->chip);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
--		return ret;
-+		goto err_pwm_add;
- 	}
- 
- 	platform_set_drvdata(pdev, pwm);
- 
- 	return 0;
-+
-+err_pwm_add:
-+	clk_disable_unprepare(pwm->bus_clk);
-+err_bus:
-+	reset_control_assert(pwm->rst);
-+
-+	return ret;
- }
- 
- static int sun4i_pwm_remove(struct platform_device *pdev)
- {
- 	struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
-+	int ret;
-+
-+	ret = pwmchip_remove(&pwm->chip);
-+	if (ret)
-+		return ret;
- 
--	return pwmchip_remove(&pwm->chip);
-+	clk_disable_unprepare(pwm->bus_clk);
-+	reset_control_assert(pwm->rst);
-+
-+	return 0;
- }
- 
- static struct platform_driver sun4i_pwm_driver = {