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authorZoltan Herpai <wigyori@uid0.hu>2016-01-09 16:20:39 +0000
committerZoltan Herpai <wigyori@uid0.hu>2016-01-09 16:20:39 +0000
commita6611a92d5f4d3bab43feb1abf36924caf3ecc87 (patch)
treebb29022fd41ba5d5bae6022bfab6f48d2c2da574 /target/linux/sunxi/patches-4.4/100-clk-sunxi-add-dram-gates-support.patch
parent24894e52bc688844dfc96fc80073f2ac3196f992 (diff)
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sunxi: initial 4.4 support
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 48161
Diffstat (limited to 'target/linux/sunxi/patches-4.4/100-clk-sunxi-add-dram-gates-support.patch')
-rw-r--r--target/linux/sunxi/patches-4.4/100-clk-sunxi-add-dram-gates-support.patch43
1 files changed, 43 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-4.4/100-clk-sunxi-add-dram-gates-support.patch b/target/linux/sunxi/patches-4.4/100-clk-sunxi-add-dram-gates-support.patch
new file mode 100644
index 0000000000..f9caaa014c
--- /dev/null
+++ b/target/linux/sunxi/patches-4.4/100-clk-sunxi-add-dram-gates-support.patch
@@ -0,0 +1,43 @@
+From 6d3a47c29186aa8d26ff05a6209c94291ace0696 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Sat, 5 Dec 2015 21:16:42 +0800
+Subject: [PATCH] clk: sunxi: Add DRAM gates support for sun4i-a10
+
+The A10/A20 share the same set of DRAM clock gates, which controls
+direct memory access for some peripherals.
+
+On the A10, bit 15 controls the system's DRAM clock output (possibly
+to the DRAM chips), which we need to keep on.
+
+On the A20 this has been moved to the DRAM controller, becoming a no-op.
+However it is still listed in the user manual, so add it anyway.
+
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
+ drivers/clk/sunxi/clk-simple-gates.c | 12 ++++++++++++
+ 2 files changed, 13 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
+index 153ac72..ef0b452 100644
+diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
+index c8acc06..f4da52b 100644
+--- a/drivers/clk/sunxi/clk-simple-gates.c
++++ b/drivers/clk/sunxi/clk-simple-gates.c
+@@ -160,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+ CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
+ sun4i_a10_ahb_init);
++
++static const int sun4i_a10_dram_critical_clocks[] __initconst = {
++ 15, /* dram_output */
++};
++
++static void __init sun4i_a10_dram_init(struct device_node *node)
++{
++ sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,
++ ARRAY_SIZE(sun4i_a10_dram_critical_clocks));
++}
++CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",
++ sun4i_a10_dram_init);