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authorZoltan Herpai <wigyori@uid0.hu>2014-08-27 12:09:46 +0000
committerZoltan Herpai <wigyori@uid0.hu>2014-08-27 12:09:46 +0000
commitf10f009609aac0941d750ae3a1106675e6d6656a (patch)
tree70f62106f833dc3b4882118e914ff183440e1e9d /target/linux/sunxi/patches-3.14/182-clk-sunxi-get-divs-parent-clockname.patch
parentb3d10005c1ce3b9676580d09001e14458e410f89 (diff)
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sunxi: initial 3.14 patchset
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 42313
Diffstat (limited to 'target/linux/sunxi/patches-3.14/182-clk-sunxi-get-divs-parent-clockname.patch')
-rw-r--r--target/linux/sunxi/patches-3.14/182-clk-sunxi-get-divs-parent-clockname.patch45
1 files changed, 45 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.14/182-clk-sunxi-get-divs-parent-clockname.patch b/target/linux/sunxi/patches-3.14/182-clk-sunxi-get-divs-parent-clockname.patch
new file mode 100644
index 0000000000..53f2217247
--- /dev/null
+++ b/target/linux/sunxi/patches-3.14/182-clk-sunxi-get-divs-parent-clockname.patch
@@ -0,0 +1,45 @@
+From 0566b74f93eaf6b2281d2605a63e06e6ba809334 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Mon, 3 Feb 2014 09:51:40 +0800
+Subject: [PATCH] clk: sunxi: get divs parent clock name from parent factor
+ clock
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Divs clocks consist of a parent factor clock with multiple outputs,
+and seperate clocks for each output. Get the name of the parent
+clock from the parent factor clock, instead of the DT node name.
+
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Mike Turquette <mturquette@linaro.org>
+Signed-off-by: Emilio López <emilio@elopez.com.ar>
+---
+ drivers/clk/sunxi/clk-sunxi.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
+index 7a2ed98..736fb60 100644
+--- a/drivers/clk/sunxi/clk-sunxi.c
++++ b/drivers/clk/sunxi/clk-sunxi.c
+@@ -869,7 +869,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
+ struct divs_data *data)
+ {
+ struct clk_onecell_data *clk_data;
+- const char *parent = node->name;
++ const char *parent;
+ const char *clk_name;
+ struct clk **clks, *pclk;
+ struct clk_hw *gate_hw, *rate_hw;
+@@ -883,6 +883,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
+
+ /* Set up factor clock that we will be dividing */
+ pclk = sunxi_factors_clk_setup(node, data->factors);
++ parent = __clk_get_name(pclk);
+
+ reg = of_iomap(node, 0);
+
+--
+2.0.3
+