sunxi: driver refresh for 3.13 - update gmac / mmc / usb / ahci drivers to follow mainline dev trees - add driver for spi - update clock support - update a31 support - move to new DT compats where appropriate - re-order patchqueue where needed - verified working a20 smp - move most DTSes off files/ - update defconfig

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>

SVN-Revision: 39782

1 files changed, 45 insertions, 0 deletions

diff --git a/target/linux/sunxi/patches-3.13/250-clk-sunxi-get-divs-parent-clkname.patch b/target/linux/sunxi/patches-3.13/250-clk-sunxi-get-divs-parent-clkname.patch
new file mode 100644
index 0000000000..4496437b8d
--- /dev/null
+++ b/target/linux/sunxi/patches-3.13/250-clk-sunxi-get-divs-parent-clkname.patch
@@ -0,0 +1,45 @@
+From 97e36b3ce3106988b82e1ca53b1d1c872bde855a Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Mon, 3 Feb 2014 09:51:40 +0800
+Subject: [PATCH] clk: sunxi: get divs parent clock name from parent factor
+ clock
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Divs clocks consist of a parent factor clock with multiple outputs,
+and seperate clocks for each output. Get the name of the parent
+clock from the parent factor clock, instead of the DT node name.
+
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Acked-by: Mike Turquette <mturquette@linaro.org>
+Signed-off-by: Emilio López <emilio@elopez.com.ar>
+---
+ drivers/clk/sunxi/clk-sunxi.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
+index 7a2ed98..736fb60 100644
+--- a/drivers/clk/sunxi/clk-sunxi.c
++++ b/drivers/clk/sunxi/clk-sunxi.c
+@@ -869,7 +869,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
+ 					struct divs_data *data)
+ {
+ 	struct clk_onecell_data *clk_data;
+-	const char *parent  = node->name;
++	const char *parent;
+ 	const char *clk_name;
+ 	struct clk **clks, *pclk;
+ 	struct clk_hw *gate_hw, *rate_hw;
+@@ -883,6 +883,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
+ 
+ 	/* Set up factor clock that we will be dividing */
+ 	pclk = sunxi_factors_clk_setup(node, data->factors);
++	parent = __clk_get_name(pclk);
+ 
+ 	reg = of_iomap(node, 0);
+ 
+-- 
+1.8.5.5
+