diff options
| author | Imre Kaloz <kaloz@openwrt.org> | 2014-02-13 13:27:14 +0000 |
|---|---|---|
| committer | Imre Kaloz <kaloz@openwrt.org> | 2014-02-13 13:27:14 +0000 |
| commit | af63cdf87ad76177fb7180e5fb57ec6f949fbb98 (patch) | |
| tree | 3f3c2ff5babca3eacef366a9b794b0ea7e5f945e /target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch | |
| parent | 83d9cec4911b6639c1c2f22cfb943df3e1252a1e (diff) | |
| download | upstream-af63cdf87ad76177fb7180e5fb57ec6f949fbb98.tar.gz upstream-af63cdf87ad76177fb7180e5fb57ec6f949fbb98.tar.bz2 upstream-af63cdf87ad76177fb7180e5fb57ec6f949fbb98.zip | |
upgrade 3.13 targets to 3.13.2, refresh patches
Signed-off-by: Imre Kaloz <kaloz@openwrt.org
SVN-Revision: 39582
Diffstat (limited to 'target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch b/target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch index 5b46d8b127..a087e3b0d3 100644 --- a/target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch +++ b/target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch @@ -13,11 +13,9 @@ Signed-off-by: Chen-Yu Tsai <wens@csie.org> drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++ 2 files changed, 58 insertions(+) -diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt -index 941bd93..79c7197 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt -@@ -36,6 +36,7 @@ Required properties: +@@ -37,6 +37,7 @@ Required properties: "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks @@ -25,11 +23,9 @@ index 941bd93..79c7197 100644 Required properties for all clocks: - reg : shall be the control register address for the clock. -diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c -index 8a07a68..df1f385 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c -@@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output) +@@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct /** @@ -77,7 +73,7 @@ index 8a07a68..df1f385 100644 * sunxi_factors_clk_setup() - Setup function for factor clocks */ -@@ -455,6 +496,14 @@ struct factors_data { +@@ -455,6 +496,14 @@ static struct clk_factors_config sun4i_m .pwidth = 2, }; @@ -92,7 +88,7 @@ index 8a07a68..df1f385 100644 static const struct factors_data sun4i_pll1_data __initconst = { .enable = 31, .table = &sun4i_pll1_config, -@@ -492,6 +541,13 @@ struct factors_data { +@@ -491,6 +540,13 @@ static const struct factors_data sun4i_m .getter = sun4i_get_mod0_factors, }; @@ -106,7 +102,7 @@ index 8a07a68..df1f385 100644 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, const struct factors_data *data) { -@@ -995,6 +1051,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, +@@ -998,6 +1054,7 @@ static const struct of_device_id clk_fac {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,}, {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,}, @@ -114,6 +110,3 @@ index 8a07a68..df1f385 100644 {} }; --- -1.8.5.1 - |