aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
diff options
context:
space:
mode:
authorZoltan Herpai <wigyori@uid0.hu>2013-11-14 23:12:52 +0000
committerZoltan Herpai <wigyori@uid0.hu>2013-11-14 23:12:52 +0000
commitf58bfd1df4e4a9b84a0e94691986c38bab6d8730 (patch)
tree9efce69525f7b07a108c03ba53b6721ebb1c8be2 /target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
parent2077361f128ff32dd6bb9fed7a4b3cd813863a9c (diff)
downloadupstream-f58bfd1df4e4a9b84a0e94691986c38bab6d8730.tar.gz
upstream-f58bfd1df4e4a9b84a0e94691986c38bab6d8730.tar.bz2
upstream-f58bfd1df4e4a9b84a0e94691986c38bab6d8730.zip
sunxi: rework target - update kernel to 3.12 - add patches for clocks, i2c, usb, sid, rtc - support common image for A10/A13/A20 - add support for a couple boards - most drivers are configured into the kernel as of now
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 38811
Diffstat (limited to 'target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch')
-rw-r--r--target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch51
1 files changed, 51 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch b/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
new file mode 100644
index 0000000000..00519b815a
--- /dev/null
+++ b/target/linux/sunxi/patches-3.12/101-clk-sunxi_add-gating-pll1.patch
@@ -0,0 +1,51 @@
+From 68557a66b206de79a4556d393d51865407525d52 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
+Date: Mon, 6 May 2013 09:59:00 -0300
+Subject: [PATCH] clk: sunxi: add gating support to PLL1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This commit adds gating support to PLL1 on the clock driver. This makes
+the PLL1 implementation fully compatible with PLL4 as well.
+
+Signed-off-by: Emilio López <emilio@elopez.com.ar>
+---
+ Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
+ drivers/clk/sunxi/clk-sunxi.c | 2 ++
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
+index 00a5c264..7d9245f 100644
+--- a/Documentation/devicetree/bindings/clock/sunxi.txt
++++ b/Documentation/devicetree/bindings/clock/sunxi.txt
+@@ -7,7 +7,7 @@ This binding uses the common clock binding[1].
+ Required properties:
+ - compatible : shall be one of the following:
+ "allwinner,sun4i-osc-clk" - for a gatable oscillator
+- "allwinner,sun4i-pll1-clk" - for the main PLL clock
++ "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
+ "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
+ "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
+ "allwinner,sun4i-axi-clk" - for the AXI clock
+diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
+index 6aed57f..c0b0675 100644
+--- a/drivers/clk/sunxi/clk-sunxi.c
++++ b/drivers/clk/sunxi/clk-sunxi.c
+@@ -293,11 +293,13 @@ struct factors_data {
+ };
+
+ static const struct factors_data sun4i_pll1_data __initconst = {
++ .enable = 31,
+ .table = &sun4i_pll1_config,
+ .getter = sun4i_get_pll1_factors,
+ };
+
+ static const struct factors_data sun6i_a31_pll1_data __initconst = {
++ .enable = 31,
+ .table = &sun6i_a31_pll1_config,
+ .getter = sun6i_a31_get_pll1_factors,
+ };
+--
+1.8.4
+