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authorMarkus Stockhausen <markus.stockhausen@gmx.de>2022-08-30 16:44:02 +0200
committerHauke Mehrtens <hauke@hauke-m.de>2022-08-31 23:25:39 +0200
commit6ff21c436dd93646f924efdd73c4b3fc59501ad3 (patch)
tree3819d5534f9ac46a7f411ca3fc10c2c4f5e37553 /target/linux/realtek
parente0753c5d5cef5b03c60601364188afb262ccd02e (diff)
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realtek: fix PLL register inconsistencies
Some devices have wrong/empty values in the PLL registers. Work around that by reporting the default values. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Diffstat (limited to 'target/linux/realtek')
-rw-r--r--target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
index c3eb270f6e..9b8183fbeb 100644
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
@@ -366,6 +366,9 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra
switch (rtcl_ccu->soc) {
case SOC_RTL838X:
+ if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB))
+ return 200000000;
+
cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1);
cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)];
break;