realtek: copy dts/files/patches/configs for 5.15

Copy dts/files/patches/configs from 5.10 to 5.15.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[refresh with updated DGS-1210 dts files]
Signed-off-by: Sander Vanheule <sander@svanheule.net>

7 files changed, 976 insertions, 0 deletions

diff --git a/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/ioremap.h
new file mode 100644
index 0000000000..c49a095792
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/ioremap.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef RTL838X_IOREMAP_H_
+#define RTL838X_IOREMAP_H_
+
+static inline int is_rtl838x_internal_registers(phys_addr_t offset)
+{
+	/* IO-Block */
+	if (offset >= 0xb8000000 && offset < 0xb9000000)
+		return 1;
+	/* Switch block */
+	if (offset >= 0xbb000000 && offset < 0xbc000000)
+		return 1;
+	return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+					 unsigned long flags)
+{
+	if (is_rtl838x_internal_registers(offset))
+		return (void __iomem *)offset;
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return is_rtl838x_internal_registers((unsigned long)addr);
+}
+
+#endif
diff --git a/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
new file mode 100644
index 0000000000..d95e5fb098
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
@@ -0,0 +1,416 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ */
+#ifndef _MACH_RTL838X_H_
+#define _MACH_RTL838X_H_
+
+#include <asm/types.h>
+/*
+ * Register access macros
+ */
+
+#define RTL838X_SW_BASE		((volatile void *) 0xBB000000)
+
+#define rtl83xx_r32(reg)	readl(reg)
+#define rtl83xx_w32(val, reg)	writel(val, reg)
+#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
+
+#define rtl83xx_r8(reg)		readb(reg)
+#define rtl83xx_w8(val, reg)	writeb(val, reg)
+
+#define sw_r32(reg)		readl(RTL838X_SW_BASE + reg)
+#define sw_w32(val, reg)	writel(val, RTL838X_SW_BASE + reg)
+#define sw_w32_mask(clear, set, reg)	\
+				sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
+#define sw_r64(reg)		((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
+				readl(RTL838X_SW_BASE + reg + 4))
+
+#define sw_w64(val, reg)	do { \
+					writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
+					writel((u32)((val) & 0xffffffff), \
+							RTL838X_SW_BASE + reg + 4); \
+				} while (0)
+
+/*
+ * SPRAM
+ */
+#define RTL838X_ISPRAM_BASE	0x0
+#define RTL838X_DSPRAM_BASE	0x0
+
+/*
+ * IRQ Controller
+ */
+#define RTL838X_IRQ_CPU_BASE	0
+#define RTL838X_IRQ_CPU_NUM	8
+#define RTL838X_IRQ_ICTL_BASE	(RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
+#define RTL838X_IRQ_ICTL_NUM	32
+
+#define RTL83XX_IRQ_UART0		31
+#define RTL83XX_IRQ_UART1		30
+#define RTL83XX_IRQ_TC0			29
+#define RTL83XX_IRQ_TC1			28
+#define RTL83XX_IRQ_OCPTO		27
+#define RTL83XX_IRQ_HLXTO		26
+#define RTL83XX_IRQ_SLXTO		25
+#define RTL83XX_IRQ_NIC			24
+#define RTL83XX_IRQ_GPIO_ABCD		23
+#define RTL83XX_IRQ_GPIO_EFGH		22
+#define RTL83XX_IRQ_RTC			21
+#define RTL83XX_IRQ_SWCORE		20
+#define RTL83XX_IRQ_WDT_IP1		19
+#define RTL83XX_IRQ_WDT_IP2		18
+
+#define RTL9300_UART1_IRQ		31
+#define RTL9300_UART0_IRQ		30
+#define RTL9300_USB_H2_IRQ		28
+#define RTL9300_NIC_IRQ			24
+#define RTL9300_SWCORE_IRQ		23
+#define RTL9300_GPIO_ABC_IRQ		13
+#define RTL9300_TC4_IRQ			11
+#define RTL9300_TC3_IRQ			10
+#define RTL9300_TC2_IRQ			 9
+#define RTL9300_TC1_IRQ			 8
+#define RTL9300_TC0_IRQ			 7
+
+
+/*
+ * MIPS32R2 counter
+ */
+#define RTL838X_COMPARE_IRQ	(RTL838X_IRQ_CPU_BASE + 7)
+
+/*
+ *  ICTL
+ *  Base address 0xb8003000UL
+ */
+#define RTL838X_ICTL1_IRQ	(RTL838X_IRQ_CPU_BASE + 2)
+#define RTL838X_ICTL2_IRQ	(RTL838X_IRQ_CPU_BASE + 3)
+#define RTL838X_ICTL3_IRQ	(RTL838X_IRQ_CPU_BASE + 4)
+#define RTL838X_ICTL4_IRQ	(RTL838X_IRQ_CPU_BASE + 5)
+#define RTL838X_ICTL5_IRQ	(RTL838X_IRQ_CPU_BASE + 6)
+
+#define GIMR			(0x00)
+#define UART0_IE		(1 << 31)
+#define UART1_IE		(1 << 30)
+#define TC0_IE			(1 << 29)
+#define TC1_IE			(1 << 28)
+#define OCPTO_IE		(1 << 27)
+#define HLXTO_IE		(1 << 26)
+#define SLXTO_IE		(1 << 25)
+#define NIC_IE			(1 << 24)
+#define GPIO_ABCD_IE		(1 << 23)
+#define GPIO_EFGH_IE		(1 << 22)
+#define RTC_IE			(1 << 21)
+#define WDT_IP1_IE		(1 << 19)
+#define WDT_IP2_IE		(1 << 18)
+
+#define GISR			(0x04)
+#define UART0_IP		(1 << 31)
+#define UART1_IP		(1 << 30)
+#define TC0_IP			(1 << 29)
+#define TC1_IP			(1 << 28)
+#define OCPTO_IP		(1 << 27)
+#define HLXTO_IP		(1 << 26)
+#define SLXTO_IP		(1 << 25)
+#define NIC_IP			(1 << 24)
+#define GPIO_ABCD_IP		(1 << 23)
+#define GPIO_EFGH_IP		(1 << 22)
+#define RTC_IP			(1 << 21)
+#define WDT_IP1_IP		(1 << 19)
+#define WDT_IP2_IP		(1 << 18)
+
+
+/* Interrupt Routing Selection */
+#define UART0_RS		2
+#define UART1_RS		1
+#define TC0_RS			5
+#define TC1_RS			1
+#define OCPTO_RS		1
+#define HLXTO_RS		1
+#define SLXTO_RS		1
+#define NIC_RS			4
+#define GPIO_ABCD_RS		4
+#define GPIO_EFGH_RS		4
+#define RTC_RS			4
+#define	SWCORE_RS		3
+#define WDT_IP1_RS		4
+#define WDT_IP2_RS		5
+
+/* Interrupt IRQ Assignments */
+#define UART0_IRQ		31
+#define UART1_IRQ		30
+#define TC0_IRQ			29
+#define TC1_IRQ			28
+#define OCPTO_IRQ		27
+#define HLXTO_IRQ		26
+#define SLXTO_IRQ		25
+#define NIC_IRQ			24
+#define GPIO_ABCD_IRQ		23
+#define GPIO_EFGH_IRQ		22
+#define RTC_IRQ			21
+#define	SWCORE_IRQ		20
+#define WDT_IP1_IRQ		19
+#define WDT_IP2_IRQ		18
+
+#define SYSTEM_FREQ		200000000
+#define RTL838X_UART0_BASE	((volatile void *)(0xb8002000UL))
+#define RTL838X_UART0_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART0_FREQ	(SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
+#define RTL838X_UART0_MAPBASE	0x18002000UL
+#define RTL838X_UART0_MAPSIZE	0x100
+#define RTL838X_UART0_IRQ	UART0_IRQ
+
+#define RTL838X_UART1_BASE	((volatile void *)(0xb8002100UL))
+#define RTL838X_UART1_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART1_FREQ	(SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
+#define RTL838X_UART1_MAPBASE	0x18002100UL
+#define RTL838X_UART1_MAPSIZE	0x100
+#define RTL838X_UART1_IRQ	UART1_IRQ
+
+#define UART0_RBR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_THR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_DLL		(RTL838X_UART0_BASE + 0x000)
+#define UART0_IER		(RTL838X_UART0_BASE + 0x004)
+#define UART0_DLM		(RTL838X_UART0_BASE + 0x004)
+#define UART0_IIR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_FCR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_LCR		(RTL838X_UART0_BASE + 0x00C)
+#define UART0_MCR		(RTL838X_UART0_BASE + 0x010)
+#define UART0_LSR		(RTL838X_UART0_BASE + 0x014)
+
+#define UART1_RBR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_THR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_DLL		(RTL838X_UART1_BASE + 0x000)
+#define UART1_IER		(RTL838X_UART1_BASE + 0x004)
+#define UART1_DLM		(RTL838X_UART1_BASE + 0x004)
+#define UART1_IIR		(RTL838X_UART1_BASE + 0x008)
+#define UART1_FCR		(RTL838X_UART1_BASE + 0x008)
+#define UART1_LCR		(RTL838X_UART1_BASE + 0x00C)
+#define UART1_MCR		(RTL838X_UART1_BASE + 0x010)
+#define UART1_LSR		(RTL838X_UART1_BASE + 0x014)
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR			0xB8001000
+#define MC_MCR_VAL		0x00000000
+
+#define MC_DCR			0xB8001004
+#define MC_DCR0_VAL		0x54480000
+
+#define MC_DTCR			0xB8001008
+#define MC_DTCR_VAL		0xFFFF05C0
+
+/*
+ * GPIO
+ */
+#define GPIO_CTRL_REG_BASE		((volatile void *) 0xb8003500)
+#define RTL838X_GPIO_PABC_CNR		(GPIO_CTRL_REG_BASE + 0x0)
+#define RTL838X_GPIO_PABC_TYPE		(GPIO_CTRL_REG_BASE + 0x04)
+#define RTL838X_GPIO_PABC_DIR		(GPIO_CTRL_REG_BASE + 0x8)
+#define RTL838X_GPIO_PABC_DATA		(GPIO_CTRL_REG_BASE + 0xc)
+#define RTL838X_GPIO_PABC_ISR		(GPIO_CTRL_REG_BASE + 0x10)
+#define RTL838X_GPIO_PAB_IMR		(GPIO_CTRL_REG_BASE + 0x14)
+#define RTL838X_GPIO_PC_IMR		(GPIO_CTRL_REG_BASE + 0x18)
+
+#define RTL930X_GPIO_CTRL_REG_BASE      ((volatile void *) 0xb8003300)
+#define RTL930X_GPIO_PABCD_DIR          (RTL930X_GPIO_CTRL_REG_BASE + 0x8)
+#define RTL930X_GPIO_PABCD_DAT          (RTL930X_GPIO_CTRL_REG_BASE + 0xc)
+#define RTL930X_GPIO_PABCD_ISR          (RTL930X_GPIO_CTRL_REG_BASE + 0x10)
+#define RTL930X_GPIO_PAB_IMR            (RTL930X_GPIO_CTRL_REG_BASE + 0x14)
+#define RTL930X_GPIO_PCD_IMR            (RTL930X_GPIO_CTRL_REG_BASE + 0x18)
+
+#define RTL838X_MODEL_NAME_INFO		(0x00D4)
+#define RTL839X_MODEL_NAME_INFO		(0x0FF0)
+#define RTL93XX_MODEL_NAME_INFO		(0x0004)
+#define RTL931X_CHIP_INFO_ADDR		(0x0008)
+
+#define RTL838X_LED_GLB_CTRL		(0xA000)
+#define RTL839X_LED_GLB_CTRL		(0x00E4)
+#define RTL9302_LED_GLB_CTRL		(0xcc00)
+#define RTL930X_LED_GLB_CTRL		(0xCC00)
+#define RTL931X_LED_GLB_CTRL		(0x0600)
+
+#define RTL838X_EXT_GPIO_DIR		(0xA08C)
+#define RTL839X_EXT_GPIO_DIR		(0x0214)
+#define RTL838X_EXT_GPIO_DATA		(0xA094)
+#define RTL839X_EXT_GPIO_DATA		(0x021c)
+#define RTL838X_EXT_GPIO_INDRT_ACCESS	(0xA09C)
+#define RTL839X_EXT_GPIO_INDRT_ACCESS	(0x0224)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+#define RTL838X_DMY_REG5		(0x0144)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+
+#define RTL838X_GMII_INTF_SEL		(0x1000)
+#define RTL838X_IO_DRIVING_ABILITY_CTRL	(0x1010)
+
+#define RTL838X_GPIO_A7		31
+#define RTL838X_GPIO_A6		30
+#define RTL838X_GPIO_A5		29
+#define RTL838X_GPIO_A4		28
+#define RTL838X_GPIO_A3		27
+#define RTL838X_GPIO_A2		26
+#define RTL838X_GPIO_A1		25
+#define RTL838X_GPIO_A0		24
+#define RTL838X_GPIO_B7		23
+#define RTL838X_GPIO_B6		22
+#define RTL838X_GPIO_B5		21
+#define RTL838X_GPIO_B4		20
+#define RTL838X_GPIO_B3		19
+#define RTL838X_GPIO_B2		18
+#define RTL838X_GPIO_B1		17
+#define RTL838X_GPIO_B0		16
+#define RTL838X_GPIO_C7		15
+#define RTL838X_GPIO_C6		14
+#define RTL838X_GPIO_C5		13
+#define RTL838X_GPIO_C4		12
+#define RTL838X_GPIO_C3		11
+#define RTL838X_GPIO_C2		10
+#define RTL838X_GPIO_C1		9
+#define RTL838X_GPIO_C0		8
+
+#define RTL838X_INT_RW_CTRL		(0x0058)
+#define RTL838X_EXT_VERSION		(0x00D0)
+#define RTL838X_PLL_CML_CTRL		(0x0FF8)
+#define RTL838X_STRAP_DBG		(0x100C)
+
+/*
+ * Reset
+ */
+#define	RGCR				(0x1E70)
+#define RTL838X_RST_GLB_CTRL_0		(0x003c)
+#define RTL838X_RST_GLB_CTRL_1		(0x0040)
+#define RTL839X_RST_GLB_CTRL		(0x0014)
+#define RTL930X_RST_GLB_CTRL_0		(0x000c)
+#define RTL931X_RST_GLB_CTRL		(0x0400)
+
+/* LED control by switch */
+#define RTL838X_LED_MODE_SEL		(0x1004)
+#define RTL838X_LED_MODE_CTRL		(0xA004)
+#define RTL838X_LED_P_EN_CTRL		(0xA008)
+
+/* LED control by software */
+#define RTL838X_LED_SW_CTRL		(0x0128)
+#define RTL839X_LED_SW_CTRL		(0xA00C)
+#define RTL838X_LED_SW_P_EN_CTRL	(0xA010)
+#define RTL839X_LED_SW_P_EN_CTRL	(0x012C)
+#define RTL838X_LED0_SW_P_EN_CTRL	(0xA010)
+#define RTL839X_LED0_SW_P_EN_CTRL	(0x012C)
+#define RTL838X_LED1_SW_P_EN_CTRL	(0xA014)
+#define RTL839X_LED1_SW_P_EN_CTRL	(0x0130)
+#define RTL838X_LED2_SW_P_EN_CTRL	(0xA018)
+#define RTL839X_LED2_SW_P_EN_CTRL	(0x0134)
+#define RTL838X_LED_SW_P_CTRL		(0xA01C)
+#define RTL839X_LED_SW_P_CTRL		(0x0144)
+
+#define RTL839X_MAC_EFUSE_CTRL		(0x02ac)
+
+/*
+ * MDIO via Realtek's SMI interface
+ */
+#define RTL838X_SMI_GLB_CTRL		(0xa100)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_0	(0xa1b8)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_1	(0xa1bc)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_2	(0xa1c0)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_3	(0xa1c4)
+#define RTL838X_SMI_PORT0_5_ADDR_CTRL	(0xa1c8)
+#define RTL838X_SMI_POLL_CTRL		(0xa17c)
+
+#define RTL839X_SMI_GLB_CTRL		(0x03f8)
+#define RTL839X_SMI_PORT_POLLING_CTRL	(0x03fc)
+#define RTL839X_PHYREG_ACCESS_CTRL	(0x03DC)
+#define RTL839X_PHYREG_CTRL		(0x03E0)
+#define RTL839X_PHYREG_PORT_CTRL	(0x03E4)
+#define RTL839X_PHYREG_DATA_CTRL	(0x03F0)
+#define RTL839X_PHYREG_MMD_CTRL		(0x3F4)
+
+#define RTL930X_SMI_GLB_CTRL		(0xCA00)
+#define RTL930X_SMI_POLL_CTRL		(0xca90)
+#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
+#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
+#define RTL930X_SMI_PORT0_5_ADDR	(0xCB80)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_0	(0xCB70)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_1	(0xCB74)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_2	(0xCB78)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_3	(0xCB7C)
+
+#define RTL931X_SMI_GLB_CTRL1		(0x0CBC)
+#define RTL931X_SMI_GLB_CTRL0		(0x0CC0)
+#define RTL931X_SMI_PORT_POLLING_CTRL	(0x0CCC)
+#define RTL931X_SMI_PORT_ADDR		(0x0C74)
+#define RTL931X_SMI_PORT_POLLING_SEL	(0x0C9C)
+#define RTL9310_SMI_PORT_POLLING_CTRL	(0x0CCC)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_0	(0x0C00)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_1	(0x0C04)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_2	(0x0C08)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_3	(0x0C10)
+#define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)
+#define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)
+#define RTL931X_MAC_L2_GLOBAL_CTRL2	(0x1358)
+#define RTL931X_MAC_L2_GLOBAL_CTRL1	(0x5548)
+
+/*
+ * Switch interrupts
+ */
+#define RTL838X_IMR_GLB			(0x1100)
+#define RTL838X_IMR_PORT_LINK_STS_CHG	(0x1104)
+#define RTL838X_ISR_GLB_SRC		(0x1148)
+#define RTL838X_ISR_PORT_LINK_STS_CHG	(0x114C)
+
+#define RTL839X_IMR_GLB			(0x0064)
+#define RTL839X_IMR_PORT_LINK_STS_CHG	(0x0068)
+#define RTL839X_ISR_GLB_SRC		(0x009c)
+#define RTL839X_ISR_PORT_LINK_STS_CHG	(0x00a0)
+
+#define RTL930X_IMR_GLB			(0xC628)
+#define RTL930X_IMR_PORT_LINK_STS_CHG	(0xC62C)
+#define RTL930X_ISR_GLB			(0xC658)
+#define RTL930X_ISR_PORT_LINK_STS_CHG	(0xC660)
+
+// IMR_GLB does not exit on RTL931X
+#define RTL931X_IMR_PORT_LINK_STS_CHG	(0x126C)
+#define RTL931X_ISR_GLB_SRC		(0x12B4)
+#define RTL931X_ISR_PORT_LINK_STS_CHG	(0x12B8)
+
+/* Definition of family IDs */
+#define RTL8389_FAMILY_ID   (0x8389)
+#define RTL8328_FAMILY_ID   (0x8328)
+#define RTL8390_FAMILY_ID   (0x8390)
+#define RTL8350_FAMILY_ID   (0x8350)
+#define RTL8380_FAMILY_ID   (0x8380)
+#define RTL8330_FAMILY_ID   (0x8330)
+#define RTL9300_FAMILY_ID   (0x9300)
+#define RTL9310_FAMILY_ID   (0x9310)
+
+/* SPI Support */
+#define RTL931X_SPI_CTRL0		(0x103C)
+
+/* Basic SoC Features */
+#define RTL838X_CPU_PORT			28
+#define RTL839X_CPU_PORT			52
+#define RTL930X_CPU_PORT			28
+#define RTL931X_CPU_PORT			56
+
+struct rtl83xx_soc_info {
+	unsigned char *name;
+	unsigned int id;
+	unsigned int family;
+	unsigned char *compatible;
+	volatile void *sw_base;
+	volatile void *icu_base;
+	int cpu_port;
+};
+
+/* rtl83xx-related functions used across subsystems */
+int rtl838x_smi_wait_op(int timeout);
+int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+
+#endif   /* _MACH_RTL838X_H_ */
diff --git a/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c b/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c
new file mode 100644
index 0000000000..1c8c30de5d
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/kernel/cevt-rtl9300.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/clockchips.h>
+#include <linux/init.h>
+#include <asm/time.h>
+#include <asm/idle.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+
+#include <mach-rtl83xx.h>
+
+/* 
+ * Timer registers
+ * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
+ */
+#define RTL9300_TC_DATA		0x0
+#define RTL9300_TC_CNT		0x4
+#define RTL9300_TC_CTRL		0x8
+#define RTL9300_TC_CTRL_MODE	BIT(24)
+#define RTL9300_TC_CTRL_EN	BIT(28)
+#define RTL9300_TC_INT		0xc
+#define RTL9300_TC_INT_IP	BIT(16)
+#define RTL9300_TC_INT_IE	BIT(20)
+
+// Timer modes
+#define TIMER_MODE_REPEAT	1
+#define TIMER_MODE_ONCE		0
+
+// Minimum divider is 2
+#define DIVISOR_RTL9300		2
+
+#define N_BITS			28
+
+#define RTL9300_CLOCK_RATE	87500000
+
+struct rtl9300_clk_dev {
+	struct clock_event_device clkdev;
+	void __iomem *base;
+};
+
+static void __iomem *rtl9300_tc_base(struct clock_event_device *clk)
+{
+	struct rtl9300_clk_dev *rtl_clk = container_of(clk, struct rtl9300_clk_dev, clkdev);
+
+	return rtl_clk->base;
+}
+
+static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
+{
+	struct rtl9300_clk_dev *rtl_clk = dev_id;
+	struct clock_event_device *clk = &rtl_clk->clkdev;
+
+	u32 v = readl(rtl_clk->base + RTL9300_TC_INT);
+
+	// Acknowledge the IRQ
+	v |= RTL9300_TC_INT_IP;
+	writel(v, rtl_clk->base + RTL9300_TC_INT);
+
+	clk->event_handler(clk);
+	return IRQ_HANDLED;
+}
+
+static void rtl9300_clock_stop(void __iomem *base)
+{
+	u32 v;
+
+	writel(0, base + RTL9300_TC_CTRL);
+
+	// Acknowledge possibly pending IRQ
+	v = readl(base + RTL9300_TC_INT);
+	writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);
+}
+
+static void rtl9300_timer_start(void __iomem *base, bool periodic)
+{
+	u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
+
+	writel(0, base + RTL9300_TC_CNT);
+	pr_debug("------------- starting timer base %08x\n", (u32)base);
+	writel(v, base + RTL9300_TC_CTRL);
+}
+
+static int rtl9300_next_event(unsigned long delta, struct clock_event_device *clk)
+{
+	void __iomem *base = rtl9300_tc_base(clk);
+
+	rtl9300_clock_stop(base);
+	writel(delta, base + RTL9300_TC_DATA);
+	rtl9300_timer_start(base, TIMER_MODE_ONCE);
+
+	return 0;
+}
+
+static int rtl9300_state_periodic(struct clock_event_device *clk)
+{
+	void __iomem *base = rtl9300_tc_base(clk);
+
+	pr_debug("------------- rtl9300_state_periodic %08x\n", (u32)base);
+	rtl9300_clock_stop(base);
+	writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);
+	rtl9300_timer_start(base, TIMER_MODE_REPEAT);
+	return 0;
+}
+
+static int rtl9300_state_oneshot(struct clock_event_device *clk)
+{
+	void __iomem *base = rtl9300_tc_base(clk);
+
+	pr_debug("------------- rtl9300_state_oneshot %08x\n", (u32)base);
+	rtl9300_clock_stop(base);
+	writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);
+	rtl9300_timer_start(base, TIMER_MODE_ONCE);
+	return 0;
+}
+
+static int rtl9300_shutdown(struct clock_event_device *clk)
+{
+	void __iomem *base = rtl9300_tc_base(clk);
+
+	pr_debug("------------- rtl9300_shutdown %08x\n", (u32)base);
+	rtl9300_clock_stop(base);
+	return 0;
+}
+
+static void rtl9300_clock_setup(void __iomem *base)
+{
+	u32 v;
+
+	// Disable timer
+	writel(0, base + RTL9300_TC_CTRL);
+
+	// Acknowledge possibly pending IRQ
+	v = readl(base + RTL9300_TC_INT);
+	writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);
+
+	// Setup maximum period (for use as clock-source)
+	writel(0x0fffffff, base + RTL9300_TC_DATA);
+}
+
+static DEFINE_PER_CPU(struct rtl9300_clk_dev, rtl9300_clockevent);
+static DEFINE_PER_CPU(char [18], rtl9300_clock_name);
+
+void rtl9300_clockevent_init(void)
+{
+	int cpu = smp_processor_id();
+	int irq;
+	struct rtl9300_clk_dev *rtl_clk = &per_cpu(rtl9300_clockevent, cpu);
+	struct clock_event_device *cd = &rtl_clk->clkdev;
+	unsigned char *name = per_cpu(rtl9300_clock_name, cpu);
+	unsigned long flags =  IRQF_PERCPU | IRQF_TIMER;
+	struct device_node *node;
+
+	pr_info("%s called for cpu%d\n", __func__, cpu);
+	BUG_ON(cpu > 3);	/* Only have 4 general purpose timers */
+
+	node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300clock");
+	if (!node) {
+		pr_err("No DT entry found for realtek,rtl9300clock\n");
+		return;
+	}
+
+	irq = irq_of_parse_and_map(node, cpu);
+	pr_info("%s using IRQ %d\n", __func__, irq);
+
+	rtl_clk->base = of_iomap(node, cpu);
+	if (!rtl_clk->base) {
+		pr_err("cannot map timer for cpu %d", cpu);
+		return;
+	}
+
+	rtl9300_clock_setup(rtl_clk->base);
+
+	sprintf(name, "rtl9300-counter-%d", cpu);
+	cd->name		= name;
+	cd->features		= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+
+	clockevent_set_clock(cd, RTL9300_CLOCK_RATE);
+
+	cd->max_delta_ns	= clockevent_delta2ns(0x0fffffff, cd);
+	cd->max_delta_ticks	= 0x0fffffff;
+	cd->min_delta_ns	= clockevent_delta2ns(0x20, cd);
+	cd->min_delta_ticks	= 0x20;
+	cd->rating		= 300;
+	cd->irq			= irq;
+	cd->cpumask		= cpumask_of(cpu);
+	cd->set_next_event	= rtl9300_next_event;
+	cd->set_state_shutdown	= rtl9300_shutdown;
+	cd->set_state_periodic	= rtl9300_state_periodic;
+	cd->set_state_oneshot	= rtl9300_state_oneshot;
+	clockevents_register_device(cd);
+
+	irq_set_affinity(irq, cd->cpumask);
+
+	if (request_irq(irq, rtl9300_timer_interrupt, flags, name, rtl_clk))
+		pr_err("Failed to request irq %d (%s)\n", irq, name);
+
+	writel(RTL9300_TC_INT_IE, rtl_clk->base + RTL9300_TC_INT);
+}
diff --git a/target/linux/realtek/files-5.15/arch/mips/rtl838x/Makefile b/target/linux/realtek/files-5.15/arch/mips/rtl838x/Makefile
new file mode 100644
index 0000000000..a9d1666d46
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/rtl838x/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the rtl838x specific parts of the kernel
+#
+
+obj-y := setup.o prom.o
diff --git a/target/linux/realtek/files-5.15/arch/mips/rtl838x/Platform b/target/linux/realtek/files-5.15/arch/mips/rtl838x/Platform
new file mode 100644
index 0000000000..9d45d2ddd5
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/rtl838x/Platform
@@ -0,0 +1,5 @@
+#
+# Realtek RTL838x SoCs
+#
+cflags-$(CONFIG_RTL83XX)   += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/
+load-$(CONFIG_RTL83XX)     += 0xffffffff80000000
diff --git a/target/linux/realtek/files-5.15/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.15/arch/mips/rtl838x/prom.c
new file mode 100644
index 0000000000..dd1b2b170d
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/rtl838x/prom.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * prom.c
+ * Early intialization code for the Realtek RTL838X SoC
+ *
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cpu.h>
+#include <asm/fw/fw.h>
+#include <asm/smp-ops.h>
+#include <asm/mips-cps.h>
+
+#include <mach-rtl83xx.h>
+
+extern char arcs_cmdline[];
+extern const char __appended_dtb;
+
+struct rtl83xx_soc_info soc_info;
+const void *fdt;
+
+#ifdef CONFIG_MIPS_MT_SMP
+extern const struct plat_smp_ops vsmp_smp_ops;
+static struct plat_smp_ops rtl_smp_ops;
+
+static void rtl_init_secondary(void)
+{
+#ifndef CONFIG_CEVT_R4K
+/*
+ * These devices are low on resources. There might be the chance that CEVT_R4K
+ * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might
+ * be active by default after startup of secondary VPE. With no registered
+ * handler that leads to continuous unhandeled interrupts. In this case disable
+ * counting (DC) in the core and confirm a pending interrupt.
+ */
+	write_c0_cause(read_c0_cause() | CAUSEF_DC);
+	write_c0_compare(0);
+#endif /* CONFIG_CEVT_R4K */
+/*
+ * Enable all CPU interrupts, as everything is managed by the external
+ * controller. TODO: Standard vsmp_init_secondary() has special treatment for
+ * Malta if external GIC is available. Maybe we need this too.
+ */
+	if (mips_gic_present())
+		pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__);
+	else
+		set_c0_status(ST0_IM);
+}
+#endif /* CONFIG_MIPS_MT_SMP */
+
+const char *get_system_type(void)
+{
+	return soc_info.name;
+}
+
+void __init prom_free_prom_memory(void)
+{
+
+}
+
+void __init device_tree_init(void)
+{
+	if (!fdt_check_header(&__appended_dtb)) {
+		fdt = &__appended_dtb;
+		pr_info("Using appended Device Tree.\n");
+	}
+	initial_boot_params = (void *)fdt;
+	unflatten_and_copy_device_tree();
+}
+
+void __init identify_rtl9302(void)
+{
+	switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {
+	case 0x93020810:
+		soc_info.name = "RTL9302A 12x2.5G";
+		break;
+	case 0x93021010:
+		soc_info.name = "RTL9302B 8x2.5G";
+		break;
+	case 0x93021810:
+		soc_info.name = "RTL9302C 16x2.5G";
+		break;
+	case 0x93022010:
+		soc_info.name = "RTL9302D 24x2.5G";
+		break;
+	case 0x93020800:
+		soc_info.name = "RTL9302A";
+		break;
+	case 0x93021000:
+		soc_info.name = "RTL9302B";
+		break;
+	case 0x93021800:
+		soc_info.name = "RTL9302C";
+		break;
+	case 0x93022000:
+		soc_info.name = "RTL9302D";
+		break;
+	case 0x93023001:
+		soc_info.name = "RTL9302F";
+		break;
+	default:
+		soc_info.name = "RTL9302";
+	}
+}
+
+void __init prom_init(void)
+{
+	uint32_t model;
+
+	/* uart0 */
+	setup_8250_early_printk_port(0xb8002000, 2, 0);
+
+	model = sw_r32(RTL838X_MODEL_NAME_INFO);
+	pr_info("RTL838X model is %x\n", model);
+	model = model >> 16 & 0xFFFF;
+
+	if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
+	    && (model != 0x8380) && (model != 0x8382)) {
+		model = sw_r32(RTL839X_MODEL_NAME_INFO);
+		pr_info("RTL839X model is %x\n", model);
+		model = model >> 16 & 0xFFFF;
+	}
+
+	if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {
+		model = sw_r32(RTL93XX_MODEL_NAME_INFO);
+		pr_info("RTL93XX model is %x\n", model);
+		model = model >> 16 & 0xFFFF;
+	}
+
+	soc_info.id = model;
+
+	switch (model) {
+	case 0x8328:
+		soc_info.name = "RTL8328";
+		soc_info.family = RTL8328_FAMILY_ID;
+		break;
+	case 0x8332:
+		soc_info.name = "RTL8332";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8380:
+		soc_info.name = "RTL8380";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8382:
+		soc_info.name = "RTL8382";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8390:
+		soc_info.name = "RTL8390";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8391:
+		soc_info.name = "RTL8391";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8392:
+		soc_info.name = "RTL8392";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8393:
+		soc_info.name = "RTL8393";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x9301:
+		soc_info.name = "RTL9301";
+		soc_info.family = RTL9300_FAMILY_ID;
+		break;
+	case 0x9302:
+		identify_rtl9302();
+		soc_info.family = RTL9300_FAMILY_ID;
+		break;
+	case 0x9303:
+		soc_info.name = "RTL9303";
+		soc_info.family = RTL9300_FAMILY_ID;
+		break;
+	case 0x9313:
+		soc_info.name = "RTL9313";
+		soc_info.family = RTL9310_FAMILY_ID;
+		break;
+	default:
+		soc_info.name = "DEFAULT";
+		soc_info.family = 0;
+	}
+
+	pr_info("SoC Type: %s\n", get_system_type());
+
+	fw_init_cmdline();
+
+	mips_cpc_probe();
+
+	if (!register_cps_smp_ops())
+		return;
+
+#ifdef CONFIG_MIPS_MT_SMP
+	if (cpu_has_mipsmt) {
+		rtl_smp_ops = vsmp_smp_ops;
+		rtl_smp_ops.init_secondary = rtl_init_secondary;
+		register_smp_ops(&rtl_smp_ops);
+		return;
+	}
+#endif
+
+	register_up_smp_ops();
+}
diff --git a/target/linux/realtek/files-5.15/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-5.15/arch/mips/rtl838x/setup.c
new file mode 100644
index 0000000000..b4d415ab44
--- /dev/null
+++ b/target/linux/realtek/files-5.15/arch/mips/rtl838x/setup.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Setup for the Realtek RTL838X SoC:
+ *	Memory, Timer and Serial
+ *
+ * Copyright (C) 2020 B. Koblitz
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ *
+ */
+
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_fdt.h>
+#include <linux/irqchip.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+
+#include "mach-rtl83xx.h"
+
+extern struct rtl83xx_soc_info soc_info;
+
+void __init plat_mem_setup(void)
+{
+	void *dtb;
+
+	set_io_port_base(KSEG1);
+
+	if (fw_passed_dtb) /* UHI interface */
+		dtb = (void *)fw_passed_dtb;
+	else if (&__dtb_start[0] != &__dtb_end[0])
+		dtb = (void *)__dtb_start;
+	else
+		panic("no dtb found");
+
+	/*
+	 * Load the devicetree. This causes the chosen node to be
+	 * parsed resulting in our memory appearing
+	 */
+	__dt_setup_arch(dtb);
+}
+
+void plat_time_init_fallback(void)
+{
+	struct device_node *np;
+	u32 freq = 500000000;
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np) {
+		pr_err("Missing 'cpus' DT node, using default frequency.");
+	} else {
+		if (of_property_read_u32(np, "frequency", &freq) < 0)
+			pr_err("No 'frequency' property in DT, using default.");
+		else
+			pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
+		of_node_put(np);
+	}
+	mips_hpt_frequency = freq / 2;
+}
+
+void __init plat_time_init(void)
+{
+/*
+ * Initialization routine resembles generic MIPS plat_time_init() with
+ * lazy error handling. The final fallback is only needed until we have
+ * converted all device trees to new clock syntax.
+ */
+	struct device_node *np;
+	struct clk *clk;
+
+	of_clk_init(NULL);
+
+	mips_hpt_frequency = 0;
+	np = of_get_cpu_node(0, NULL);
+	if (!np) {
+		pr_err("Failed to get CPU node\n");
+	} else {
+		clk = of_clk_get(np, 0);
+		if (IS_ERR(clk)) {
+			pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
+		} else {
+			mips_hpt_frequency = clk_get_rate(clk) / 2;
+			clk_put(clk);
+		}
+	}
+
+	if (!mips_hpt_frequency)
+		plat_time_init_fallback();
+
+	timer_probe();
+}
+
+void __init arch_init_irq(void)
+{
+	irqchip_init();
+}