diff options
author | Birger Koblitz <git@birger-koblitz.de> | 2021-09-08 20:00:31 +0200 |
---|---|---|
committer | John Crispin <john@phrozen.org> | 2021-10-09 08:25:06 +0200 |
commit | 28e972b2ea2f55a593defcbd2dc21710cce648c7 (patch) | |
tree | de8ba964ea7b239ea84d61e3ab1a16b1be11854a /target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h | |
parent | 9d9bf16aa8d966834ac1280f96c37d22552c33d1 (diff) | |
download | upstream-28e972b2ea2f55a593defcbd2dc21710cce648c7.tar.gz upstream-28e972b2ea2f55a593defcbd2dc21710cce648c7.tar.bz2 upstream-28e972b2ea2f55a593defcbd2dc21710cce648c7.zip |
realtek: Configure initial L2 learning setup
Configure a sane L2 learning configuration upon DSA driver load so that the
switch can start learning L2 addresses. Also configure the correct flood masks
for broadcast and unknown unicast traffice.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Diffstat (limited to 'target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h')
-rw-r--r-- | target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h index e695879da1..6ff59c4348 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h @@ -198,6 +198,15 @@ #define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) #define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) +#define RTL838X_L2_LRN_CONSTRT (0x329C) +#define RTL839X_L2_LRN_CONSTRT (0x3910) +#define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c) +#define RTL838X_L2_FLD_PMSK (0x3288) +#define RTL839X_L2_FLD_PMSK (0x38EC) +#define RTL930X_L2_BC_FLD_PMSK (0x9068) +#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) +#define RTL838X_L2_LRN_CONSTRT_EN (0x3368) + #define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) #define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) #define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2))) @@ -303,6 +312,8 @@ /* 802.1X */ #define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988) #define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C) +#define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C) +#define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060) /* QoS */ #define RTL838X_QM_INTPRI2QID_CTRL (0x5F00) @@ -699,6 +710,7 @@ struct rtl838x_reg { int (*pie_rule_write)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr); int (*pie_rule_add)(struct rtl838x_switch_priv *priv, struct pie_rule *rule); void (*pie_rule_rm)(struct rtl838x_switch_priv *priv, struct pie_rule *rule); + void (*l2_learning_setup)(void); u32 (*packet_cntr_read)(int counter); void (*packet_cntr_clear)(int counter); }; |