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authorFlorian Fainelli <florian@openwrt.org>2008-07-15 17:18:28 +0000
committerFlorian Fainelli <florian@openwrt.org>2008-07-15 17:18:28 +0000
commitb0250695a9247aac244b770a0fb0d6deaad5467c (patch)
tree2bb27977d90b0912abb949aa056003cba3a00e09 /target/linux/rb532/files
parent714a721010caa3941e7e178944c9e843c2108b59 (diff)
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Add basic 2.6.24 support for rb532, korina napi code has to be adapted to work
SVN-Revision: 11844
Diffstat (limited to 'target/linux/rb532/files')
-rw-r--r--target/linux/rb532/files/include/asm-mips/rc32434/war.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/rb532/files/include/asm-mips/rc32434/war.h b/target/linux/rb532/files/include/asm-mips/rc32434/war.h
new file mode 100644
index 0000000000..3ddf187e98
--- /dev/null
+++ b/target/linux/rb532/files/include/asm-mips/rc32434/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 1
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */