diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2006-12-19 08:16:35 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2006-12-19 08:16:35 +0000 |
| commit | b488718665292ce8667e19f7f99f5a50cb25a4f6 (patch) | |
| tree | 556c5c4b9d367240fea43af8022aae9dc3ce3ec6 /target/linux/rb532-2.6/patches | |
| parent | e6c48573c5c99d377cd2a7e22462d406719dfa5d (diff) | |
| download | upstream-b488718665292ce8667e19f7f99f5a50cb25a4f6.tar.gz upstream-b488718665292ce8667e19f7f99f5a50cb25a4f6.tar.bz2 upstream-b488718665292ce8667e19f7f99f5a50cb25a4f6.zip | |
first round of rb532 cleanup
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@5855 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/rb532-2.6/patches')
| -rw-r--r-- | target/linux/rb532-2.6/patches/100-rb5xx_support.patch | 2139 |
1 files changed, 99 insertions, 2040 deletions
diff --git a/target/linux/rb532-2.6/patches/100-rb5xx_support.patch b/target/linux/rb532-2.6/patches/100-rb5xx_support.patch index 0dda2407be..43e68c01b2 100644 --- a/target/linux/rb532-2.6/patches/100-rb5xx_support.patch +++ b/target/linux/rb532-2.6/patches/100-rb5xx_support.patch @@ -567,9 +567,10 @@ diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,214 @@ +@@ -0,0 +1,210 @@ +/* + * RouterBoard 500 Platform devices ++ * + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify @@ -777,214 +778,6 @@ diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices. +arch_initcall(plat_setup_devices); + + -+#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS) -+extern void block2mtd_setup(char *initstr); -+extern void mount_devfs_fs(void); -+ -+#endif -diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c ---- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/rb500/early_serial.c 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,199 @@ -+/************************************************************************** -+ * -+ * BRIEF MODULE DESCRIPTION -+ * EB434 specific polling driver for 16550 UART. -+ * -+ * Copyright 2004 IDT Inc. (rischelp@idt.com) -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ ************************************************************************** -+ * Copyright (C) 2000 by Lineo, Inc. -+ * Written by Quinn Jensen (jensenq@lineo.com) -+ ************************************************************************** -+ * P. Sadik Oct 20, 2003 -+ * -+ * DIVISOR is made a function of idt_cpu_freq -+ ************************************************************************** -+ * P. Sadik Oct 30, 2003 -+ * -+ * added reset_cons_port -+ ************************************************************************** -+ */ -+ -+#include <linux/serial_reg.h> -+ -+/* turn this on to watch the debug protocol echoed on the console port */ -+#define DEBUG_REMOTE_DEBUG -+ -+#define CONS_BAUD 115200 -+ -+extern unsigned int idt_cpu_freq; -+ -+#define EXT_FREQ 24000000 -+#define INT_FREQ idt_cpu_freq -+ -+#define EXT_PORT 0xb9800000u -+#define EXT_SHIFT 0 -+ -+#ifdef __MIPSEB__ -+#define INT_PORT 0xb8058003u -+#else -+#define INT_PORT 0xb8058000u -+#endif -+#define INT_SHIFT 2 -+ -+#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14 -+#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT -+ -+typedef struct -+{ -+ volatile unsigned char *base; -+ unsigned int shift; -+ unsigned int freq; -+ unsigned int fcr; -+} ser_port; -+ -+ser_port ports[2] = -+{ -+ { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR}, -+ { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR} -+}; -+ -+#define CONS_PORT 0 -+ -+void cons_putc(char c); -+int port_getc(int port); -+void port_putc(int port, char c); -+ -+int cons_getc(void) -+{ -+ return port_getc(CONS_PORT); -+} -+ -+void cons_putc(char c) -+{ -+ port_putc(CONS_PORT, c); -+} -+ -+void cons_puts(char *s) -+{ -+ while(*s) { -+ if(*s == '\n') cons_putc('\r'); -+ cons_putc(*s); -+ s++; -+ } -+} -+ -+void cons_do_putn(int n) -+{ -+ if(n) { -+ cons_do_putn(n / 10); -+ cons_putc(n % 10 + '0'); -+ } -+} -+ -+void cons_putn(int n) -+{ -+ if(n < 0) { -+ cons_putc('-'); -+ n = -n; -+ } -+ -+ if (n == 0) { -+ cons_putc('0'); -+ } else { -+ cons_do_putn(n); -+ } -+} -+ -+int port_getc(int p) -+{ -+ volatile unsigned char *port = ports[p].base; -+ int s = ports[p].shift; -+ int c; -+ -+ while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) { -+ continue; -+ } -+ -+ c = *(port + (UART_RX << s)); -+ -+ return c; -+} -+ -+int port_getc_ready(int p) -+{ -+ volatile unsigned char *port = ports[p].base; -+ int s = ports[p].shift; -+ -+ return *(port + (UART_LSR << s)) & UART_LSR_DR; -+} -+ -+#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE) -+ -+void port_putc(int p, char c) -+{ -+ volatile unsigned char *port = ports[p].base; -+ int s = ports[p].shift; -+ volatile unsigned char *lsr = port + (UART_LSR << s); -+ -+ while((*lsr & OK_TO_XMT) != OK_TO_XMT) { -+ continue; -+ } -+ -+ *(port + (UART_TX << s)) = c; -+} -+ -+void reset_cons_port(void) -+{ -+ volatile unsigned char *port = ports[CONS_PORT].base; -+ unsigned int s = ports[CONS_PORT].shift; -+ unsigned int DIVISOR; -+ -+ if (ports[CONS_PORT].freq) -+ DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD); -+ else -+ DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD); -+ -+ /* reset the port */ -+ *(port + (UART_CSR << s)) = 0; -+ -+ /* clear and enable the FIFOs */ -+ *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr; -+ -+ /* set the baud rate */ -+ *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */ -+ -+ *(port + (UART_DLL << s)) = DIVISOR; -+ *(port + (UART_DLM << s)) = DIVISOR >> 8; -+ /* set the line control stuff and disable DLL, DLM regs */ -+ -+ *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */ -+ UART_LCR_WLEN8; /* 8 bit word length */ -+ -+ /* leave interrupts off */ -+ *(port + (UART_IER << s)) = 0; -+ -+ /* the modem controls don't leave the chip on this port, so leave them alone */ -+ *(port + (UART_MCR << s)) = 0; -+} diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/arch/mips/rb500/irq.c 2006-12-14 04:14:16.000000000 +0100 @@ -1261,7 +1054,7 @@ diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile +# Makefile for the RB500 board specific parts of the kernel +# + -+obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o ++obj-y += irq.o time.o setup.o serial.o prom.o misc.o devices.o diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/arch/mips/rb500/misc.c 2006-12-14 04:09:50.000000000 +0100 @@ -1325,7 +1118,7 @@ diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/arch/mips/rb500/prom.c 2006-12-14 05:15:05.000000000 +0100 -@@ -0,0 +1,181 @@ +@@ -0,0 +1,161 @@ +/* +* prom.c +********************************************************************** @@ -1367,8 +1160,6 @@ diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c + +#define PROM_ENTRY(x) (0xbfc00000+((x)*8)) +extern void __init setup_serial_port(void); -+extern void cons_putc(char c); -+extern void cons_puts(char *s); + +unsigned int idt_cpu_freq = 132000000; +EXPORT_SYMBOL(idt_cpu_freq); @@ -1413,24 +1204,6 @@ diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c + +void __init prom_setup_cmdline(void); + -+#ifdef DEBUG_DDR -+void cons_puthex4(u32 h){ -+ h&=0x0f; -+ if (h>=10) -+ cons_putc((h-10)+'a'); -+ else -+ cons_putc(h+'0'); -+} -+ -+void cons_putreg32(u32 reg){ -+ char c; -+ cons_putc('0'); -+ cons_putc('x'); -+ for (c=28;c>=0;c-=4) -+ cons_puthex4(reg>>c); -+} -+#endif -+ +void __init prom_init(void) +{ + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */ @@ -1510,7 +1283,7 @@ diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/arch/mips/rb500/serial.c 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,79 @@ +@@ -0,0 +1,77 @@ +/************************************************************************** + * + * BRIEF MODULE DESCRIPTION @@ -1583,10 +1356,8 @@ diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c +{ + serial_req.uartclk = idt_cpu_freq; + -+ if (early_serial_setup(&serial_req)){ -+ cons_puts("Serial setup failed!\n"); ++ if (early_serial_setup(&serial_req)) + return -ENODEV; -+ } + + return(0); +} @@ -1772,104 +1543,6 @@ diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c + write_c0_compare(r4k_cur); +} + -diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c ---- linux.old/drivers/mtd/devices/block2mtd.c 2006-11-29 22:57:37.000000000 +0100 -+++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-12-14 04:09:50.000000000 +0100 -@@ -26,7 +26,6 @@ - #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args) - #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args) - -- - /* Info for the block device */ - struct block2mtd_dev { - struct list_head list; -@@ -106,7 +105,7 @@ - - while (pages) { - page = page_readahead(mapping, index); -- if (!page) -+ if (!page || !page_address(page)) - return -ENOMEM; - if (IS_ERR(page)) - return PTR_ERR(page); -@@ -287,7 +286,7 @@ - - - /* FIXME: ensure that mtd->size % erase_size == 0 */ --static struct block2mtd_dev *add_device(char *devname, int erase_size) -+static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias) - { - struct block_device *bdev; - struct block2mtd_dev *dev; -@@ -330,14 +329,15 @@ - - /* Setup the MTD structure */ - /* make the name contain the block device in */ -- dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname), -+ dev->mtd.name = kmalloc(strlen((alias ?: devname)), - GFP_KERNEL); - if (!dev->mtd.name) - goto devinit_err; - -- sprintf(dev->mtd.name, "block2mtd: %s", devname); -+ strcpy(dev->mtd.name, (alias ?: devname)); - - dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; -+ dev->mtd.size -= dev->mtd.size % erase_size; - dev->mtd.erasesize = erase_size; - dev->mtd.writesize = 1; - dev->mtd.type = MTD_RAM; -@@ -356,7 +356,7 @@ - } - list_add(&dev->list, &blkmtd_device_list); - INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index, -- dev->mtd.name + strlen("blkmtd: "), -+ dev->mtd.name, - dev->mtd.erasesize >> 10, dev->mtd.erasesize); - return dev; - -@@ -432,7 +432,7 @@ - { - char buf[80 + 12]; /* 80 for device, 12 for erase size */ - char *str = buf; -- char *token[2]; -+ char *token[3]; - char *name; - size_t erase_size = PAGE_SIZE; - int i, ret; -@@ -443,7 +443,7 @@ - strcpy(str, val); - kill_final_newline(str); - -- for (i = 0; i < 2; i++) -+ for (i = 0; i < 3; i++) - token[i] = strsep(&str, ","); - - if (str) -@@ -464,13 +464,13 @@ - } - } - -- add_device(name, erase_size); -+ add_device(name, erase_size, token[2]); - - return 0; - } - - --static int block2mtd_setup(const char *val, struct kernel_param *kp) -+int block2mtd_setup(const char *val, struct kernel_param *kp) - { - #ifdef MODULE - return block2mtd_setup2(val); -@@ -499,6 +499,7 @@ - - module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); - MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\""); -+EXPORT_SYMBOL(block2mtd_setup); - - static int __init block2mtd_init(void) - { diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile --- linux.old/drivers/pci/Makefile 2006-11-29 22:57:37.000000000 +0100 +++ linux.dev/drivers/pci/Makefile 2006-12-14 04:09:50.000000000 +0100 @@ -1906,112 +1579,10 @@ diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h /* * ISA Level encodings -diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h ---- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/crom.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,98 @@ -+#ifndef __IDT_CROM_H__ -+#define __IDT_CROM_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Configuration ROM register definitions. -+ * -+ * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020118 -+ * Update : -+ * $Log: crom.h,v $ -+ * Revision 1.2 2002/06/06 18:34:03 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.1 2002/05/29 17:33:21 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ CROM0_PhysicalAddress = 0x100b8000, -+ CROM_PhysicalAddress = CROM0_PhysicalAddress, -+ -+ CROM0_VirtualAddress = 0xb00b8000, -+ CROM_VirtualAddress = CROM0_VirtualAddress, -+} ; -+ -+typedef struct CROM_s -+{ -+ U32 cromw0 ; // use CROMW0_ -+ U32 cromw1 ; // use CROMW1_ -+ U32 cromw2 ; // use CROMW2_ -+} volatile * CROM_t ; -+ -+enum -+{ -+ CROMW0_xloc_b = 0, -+ CROMW0_xloc_m = 0x0000003f, -+ CROMW0_yloc_b = 8, -+ CROMW0_yloc_m = 0x00003f00, -+ CROMW0_speed_b = 16, -+ CROMW0_speed_m = 0x01ff0000, -+ CROMW1_wafer_b = 0, -+ CROMW1_wafer_m = 0x0000001f, -+ CROMW1_lot_b = 8, -+ CROMW1_lot_m = 0x0fffff00, -+ CROMW1_fab_b = 28, -+ CROMW1_fab_m = 0xf0000000, -+ CROMW2_pci_b = 0, -+ CROMW2_pci_m = 0x00000001, -+ CROMW2_eth0_b = 1, -+ CROMW2_eth0_m = 0x00000002, -+ CROMW2_eth1_b = 2, -+ CROMW2_eth1_m = 0x00000004 -+ CROMW2_i2c_b = 3, -+ CROMW2_i2c_m = 0x00000008, -+ CROMW2_rng_b = 4, -+ CROMW2_rng_m = 0x00000010, -+ CROMW2_se_b = 5, -+ CROMW2_se_m = 0x00000020, -+ CROMW2_des_b = 6, -+ CROMW2_des_m = 0x00000040, -+ CROMW2_tdes_b = 7, -+ CROMW2_tdes_m = 0x00000080, -+ CROMW2_a128_b = 8, -+ CROMW2_a128_m = 0x00000100, -+ CROMW2_a192_b = 9, -+ CROMW2_a192_m = 0x00000200, -+ CROMW2_a256_b = 10, -+ CROMW2_a256_m = 0x00000400, -+ CROMW2_md5_b = 11, -+ CROMW2_md5_m = 0x00000800, -+ CROMW2_s1_b = 12, -+ CROMW2_s1_m = 0x00001000, -+ CROMW2_s256_b = 13, -+ CROMW2_s256_m = 0x00002000, -+ CROMW2_pka_b = 14, -+ CROMW2_pka_m = 0x00004000, -+ CROMW2_exp_b = 15, -+ CROMW2_exp_m = 0x00018000, -+ CROMW2_exp_8192_v = 0, -+ CROMW2_exp_1536_v = 1, -+ CROMW2_exp_1024_v = 2, -+ CROMW2_exp_512_v = 3, -+ CROMW2_rocfg_b = 17, -+ CROMW2_rocfg_m = 0x000e0000, -+} ; -+ -+#endif // __IDT_CROM_H__ diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,175 @@ +@@ -0,0 +1,173 @@ +#ifndef __IDT_DDR_H__ +#define __IDT_DDR_H__ + @@ -2037,8 +1608,6 @@ diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc + * + ******************************************************************************/ + -+#include <asm/rc32434/types.h> -+ +enum +{ + DDR0_PhysicalAddress = 0x18018000, @@ -2050,17 +1619,17 @@ diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc + +typedef struct DDR_s +{ -+ U32 ddrbase ; -+ U32 ddrmask ; -+ U32 res1; -+ U32 res2; -+ U32 ddrc ; -+ U32 ddrabase ; -+ U32 ddramask ; -+ U32 ddramap ; -+ U32 ddrcust; -+ U32 ddrrdc; -+ U32 ddrspare; ++ u32 ddrbase ; ++ u32 ddrmask ; ++ u32 res1; ++ u32 res2; ++ u32 ddrc ; ++ u32 ddrabase ; ++ u32 ddramask ; ++ u32 ddramap ; ++ u32 ddrcust; ++ u32 ddrrdc; ++ u32 ddrspare; +} volatile *DDR_t ; + +enum @@ -2190,7 +1759,7 @@ diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,134 @@ +@@ -0,0 +1,132 @@ +#ifndef __IDT_DEV_H__ +#define __IDT_DEV_H__ + @@ -2216,8 +1785,6 @@ diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc + * + ******************************************************************************/ + -+#include <asm/rc32434/types.h> -+ +enum +{ + DEV0_PhysicalAddress = 0x18010000, @@ -2229,10 +1796,10 @@ diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc + +typedef struct DEVICE_s +{ -+ U32 devbase ; // Device Base -+ U32 devmask ; // Device Mask -+ U32 devc ; // Device Control -+ U32 devtc ; // Device Timing Control ++ u32 devbase ; // Device Base ++ u32 devmask ; // Device Mask ++ u32 devc ; // Device Control ++ u32 devtc ; // Device Timing Control +} volatile *DEVICE_t ; + +enum @@ -2243,13 +1810,13 @@ diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc +typedef struct DEV_s +{ + struct DEVICE_s dev [DEV_Count] ; -+ U32 btcs ; // Bus timeout control / status -+ U32 btcompare ; // Compare -+ U32 btaddr ; // Timeout address. -+ U32 devdacs ; // Decoupled access control. -+ U32 devdaa ; // Decoupled access address. -+ U32 devdad ; // Decoupled access address. -+ U32 devspare ; // spare. ++ u32 btcs ; // Bus timeout control / status ++ u32 btcompare ; // Compare ++ u32 btaddr ; // Timeout address. ++ u32 devdacs ; // Decoupled access control. ++ u32 devdaa ; // Decoupled access address. ++ u32 devdad ; // Decoupled access address. ++ u32 devspare ; // spare. +} volatile *DEV_t ; + +enum @@ -2328,7 +1895,7 @@ diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,202 @@ +@@ -0,0 +1,201 @@ +#ifndef __IDT_DMA_H__ +#define __IDT_DMA_H__ + @@ -2357,7 +1924,6 @@ diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc + * + ******************************************************************************/ + -+#include <asm/rc32434/types.h> +enum +{ + DMA0_PhysicalAddress = 0x18040000, @@ -2373,10 +1939,10 @@ diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc + +typedef struct DMAD_s +{ -+ U32 control ; // Control. use DMAD_* -+ U32 ca ; // Current Address. -+ U32 devcs ; // Device control and status. -+ U32 link ; // Next descriptor in chain. ++ u32 control ; // Control. use DMAD_* ++ u32 ca ; // Current Address. ++ u32 devcs ; // Device control and status. ++ u32 link ; // Next descriptor in chain. +} volatile *DMAD_t ; + +enum @@ -2425,11 +1991,11 @@ diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc + +struct DMA_Chan_s +{ -+ U32 dmac ; // Control. -+ U32 dmas ; // Status. -+ U32 dmasm ; // Mask. -+ U32 dmadptr ; // Descriptor pointer. -+ U32 dmandptr ; // Next descriptor pointer. ++ u32 dmac ; // Control. ++ u32 dmas ; // Status. ++ u32 dmasm ; // Mask. ++ u32 dmadptr ; // Descriptor pointer. ++ u32 dmandptr ; // Next descriptor pointer. +}; + +typedef struct DMA_Chan_s volatile *DMA_Chan_t ; @@ -2534,7 +2100,7 @@ diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,73 @@ +@@ -0,0 +1,72 @@ +#ifndef __IDT_DMA_V_H__ +#define __IDT_DMA_V_H__ + @@ -2562,7 +2128,6 @@ diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/ + * + * + ******************************************************************************/ -+#include <asm/rc32434/types.h> +#include <asm/rc32434/dma.h> +#include <asm/rc32434/rc32434.h> +#define DMA_CHAN_OFFSET 0x14 @@ -2611,7 +2176,7 @@ diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/ diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,322 @@ +@@ -0,0 +1,320 @@ +#ifndef __IDT_ETH_H__ +#define __IDT_ETH_H__ + @@ -2639,8 +2204,6 @@ diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc + * + ******************************************************************************/ + -+#include <asm/rc32434/types.h> -+ +enum +{ + ETH0_PhysicalAddress = 0x18060000, @@ -2652,51 +2215,51 @@ diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc + +typedef struct +{ -+ U32 ethintfc ; -+ U32 ethfifott ; -+ U32 etharc ; -+ U32 ethhash0 ; -+ U32 ethhash1 ; -+ U32 ethu0 [4] ; // Reserved. -+ U32 ethpfs ; -+ U32 ethmcp ; -+ U32 eth_u1 [10] ; // Reserved. -+ U32 ethspare ; -+ U32 eth_u2 [42] ; // Reserved. -+ U32 ethsal0 ; -+ U32 ethsah0 ; -+ U32 ethsal1 ; -+ U32 ethsah1 ; -+ U32 ethsal2 ; -+ U32 ethsah2 ; -+ U32 ethsal3 ; -+ U32 ethsah3 ; -+ U32 ethrbc ; -+ U32 ethrpc ; -+ U32 ethrupc ; -+ U32 ethrfc ; -+ U32 ethtbc ; -+ U32 ethgpf ; -+ U32 eth_u9 [50] ; // Reserved. -+ U32 ethmac1 ; -+ U32 ethmac2 ; -+ U32 ethipgt ; -+ U32 ethipgr ; -+ U32 ethclrt ; -+ U32 ethmaxf ; -+ U32 eth_u10 ; // Reserved. -+ U32 ethmtest ; -+ U32 miimcfg ; -+ U32 miimcmd ; -+ U32 miimaddr ; -+ U32 miimwtd ; -+ U32 miimrdd ; -+ U32 miimind ; -+ U32 eth_u11 ; // Reserved. -+ U32 eth_u12 ; // Reserved. -+ U32 ethcfsa0 ; -+ U32 ethcfsa1 ; -+ U32 ethcfsa2 ; ++ u32 ethintfc ; ++ u32 ethfifott ; ++ u32 etharc ; ++ u32 ethhash0 ; ++ u32 ethhash1 ; ++ u32 ethu0 [4] ; // Reserved. ++ u32 ethpfs ; ++ u32 ethmcp ; ++ u32 eth_u1 [10] ; // Reserved. ++ u32 ethspare ; ++ u32 eth_u2 [42] ; // Reserved. ++ u32 ethsal0 ; ++ u32 ethsah0 ; ++ u32 ethsal1 ; ++ u32 ethsah1 ; ++ u32 ethsal2 ; ++ u32 ethsah2 ; ++ u32 ethsal3 ; ++ u32 ethsah3 ; ++ u32 ethrbc ; ++ u32 ethrpc ; ++ u32 ethrupc ; ++ u32 ethrfc ; ++ u32 ethtbc ; ++ u32 ethgpf ; ++ u32 eth_u9 [50] ; // Reserved. ++ u32 ethmac1 ; ++ u32 ethmac2 ; ++ u32 ethipgt ; ++ u32 ethipgr ; ++ u32 ethclrt ; ++ u32 ethmaxf ; ++ u32 eth_u10 ; // Reserved. ++ u32 ethmtest ; ++ u32 miimcfg ; ++ u32 miimcmd ; ++ u32 miimaddr ; ++ u32 miimwtd ; ++ u32 miimrdd ; ++ u32 miimind ; ++ u32 eth_u11 ; // Reserved. ++ u32 eth_u12 ; // Reserved. ++ u32 ethcfsa0 ; ++ u32 ethcfsa1 ; ++ u32 ethcfsa2 ; +} volatile *ETH_t; + +enum @@ -2937,7 +2500,7 @@ diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,64 @@ +@@ -0,0 +1,63 @@ +#ifndef __IDT_ETH_V_H__ +#define __IDT_ETH_V_H__ + @@ -2965,7 +2528,6 @@ diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/ + * + ******************************************************************************/ + -+#include <asm/rc32434/types.h> +#include <asm/rc32434/eth.h> + +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */ @@ -3005,7 +2567,7 @@ diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/ diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,182 @@ +@@ -0,0 +1,181 @@ +#ifndef __IDT_GPIO_H__ +#define __IDT_GPIO_H__ + @@ -3031,7 +2593,6 @@ diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/r + * + ******************************************************************************/ + -+#include <asm/rc32434/types.h> +enum +{ + GPIO0_PhysicalAddress = 0x18050000, @@ -3043,25 +2604,25 @@ diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/r + +typedef struct +{ -+ U32 gpiofunc; /* GPIO Function Register ++ u32 gpiofunc; /* GPIO Function Register + * gpiofunc[x]==0 bit = gpio + * func[x]==1 bit = altfunc + */ -+ U32 gpiocfg; /* GPIO Configuration Register ++ u32 gpiocfg; /* GPIO Configuration Register + * gpiocfg[x]==0 bit = input + * gpiocfg[x]==1 bit = output + */ -+ U32 gpiod; /* GPIO Data Register ++ u32 gpiod; /* GPIO Data Register + * gpiod[x] read/write gpio pinX status + */ -+ U32 gpioilevel; /* GPIO Interrupt Status Register ++ u32 gpioilevel; /* GPIO Interrupt Status Register + * interrupt level (see gpioistat) + */ -+ U32 gpioistat; /* Gpio Interrupt Status Register ++ u32 gpioistat; /* Gpio Interrupt Status Register + * istat[x] = (gpiod[x] == level[x]) + * cleared in ISR (STICKY bits) + */ -+ U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ ++ u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ +} volatile * GPIO_t ; + +typedef enum @@ -3188,568 +2749,6 @@ diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/r + +#endif // __IDT_GPIO_H__ + -diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h ---- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,147 @@ -+#ifndef __IDT_I2C_H__ -+#define __IDT_I2C_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * I2C register definitions. -+ * -+ * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020120 -+ * Update : -+ * $Log: i2c.h,v $ -+ * Revision 1.2 2002/06/06 18:34:04 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.1 2002/05/29 17:33:22 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ I2C0_PhysicalAddress = 0x18068000, -+ I2C_PhysicalAddress = I2C0_PhysicalAddress, -+ -+ I2C0_VirtualAddress = 0xb8068000, -+ I2C_VirtualAddress = I2C0_VirtualAddress, -+} ; -+ -+typedef struct -+{ -+ U32 i2cc ; -+ U32 i2cdi ; -+ U32 i2cdo ; -+ U32 i2ccp ; // I2C clk = ICLK / div / 8 -+ U32 i2cmcmd ; -+ U32 i2cms ; -+ U32 i2cmsm ; -+ U32 i2css ; -+ U32 i2cssm ; -+ U32 i2csaddr ; -+ U32 i2csack ; -+} volatile * I2C_t ; -+enum -+{ -+ I2CC_men_b = 0, // In I2C-> i2cc -+ I2CC_men_m = 0x00000001, -+ I2CC_sen_b = 1, // In I2C-> i2cc -+ I2CC_sen_m = 0x00000002, -+ I2CC_iom_b = 2, // In I2C-> i2cc -+ I2CC_iom_m = 0x00000004, -+ -+ I2CDI_data_b = 0, // In I2C-> i2cdi -+ I2CDI_data_m = 0x000000ff, -+ -+ I2CDO_data_b = 0, // In I2C-> i2cdo -+ I2CDO_data_m = 0x000000ff, -+ -+ I2CCP_div_b = 0, // In I2C-> i2ccp -+ I2CCP_div_m = 0x0000ffff, -+ -+ I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd -+ I2CMCMD_cmd_m = 0x0000000f, -+ I2CMCMD_cmd_nop_v = 0, -+ I2CMCMD_cmd_start_v = 1, -+ I2CMCMD_cmd_stop_v = 2, -+ I2CMCMD_cmd_res3_v = 3, -+ I2CMCMD_cmd_rd_v = 4, -+ I2CMCMD_cmd_rdack_v = 5, -+ I2CMCMD_cmd_wd_v = 6, -+ I2CMCMD_cmd_wdack_v = 7, -+ I2CMCMD_cmd_res8_v = 8, -+ I2CMCMD_cmd_res9_v = 9, -+ I2CMCMD_cmd_res10_v = 10, -+ I2CMCMD_cmd_res11_v = 11, -+ I2CMCMD_cmd_res12_v = 12, -+ I2CMCMD_cmd_res13_v = 13, -+ I2CMCMD_cmd_res14_v = 14, -+ I2CMCMD_cmd_res15_v = 15, -+ -+ I2CMS_d_b = 0, // In I2C-> i2cms -+ I2CMS_d_m = 0x00000001, -+ I2CMS_na_b = 1, // In I2C-> i2cms -+ I2CMS_na_m = 0x00000002, -+ I2CMS_la_b = 2, // In I2C-> i2cms -+ I2CMS_la_m = 0x00000004, -+ I2CMS_err_b = 3, // In I2C-> i2cms -+ I2CMS_err_m = 0x00000008, -+ -+ I2CMSM_d_b = 0, // In I2C-> i2cmsm -+ I2CMSM_d_m = 0x00000001, -+ I2CMSM_na_b = 1, // In I2C-> i2cmsm -+ I2CMSM_na_m = 0x00000002, -+ I2CMSM_la_b = 2, // In I2C-> i2cmsm -+ I2CMSM_la_m = 0x00000004, -+ I2CMSM_err_b = 3, // In I2C-> i2cmsm -+ I2CMSM_err_m = 0x00000008, -+ -+ I2CSS_rr_b = 0, // In I2C-> i2css -+ I2CSS_rr_m = 0x00000001, -+ I2CSS_wr_b = 1, // In I2C-> i2css -+ I2CSS_wr_m = 0x00000002, -+ I2CSS_sa_b = 2, // In I2C-> i2css -+ I2CSS_sa_m = 0x00000004, -+ I2CSS_tf_b = 3, // In I2C-> i2css -+ I2CSS_tf_m = 0x00000008, -+ I2CSS_gc_b = 4, // In I2C-> i2css -+ I2CSS_gc_m = 0x00000010, -+ I2CSS_na_b = 5, // In I2C-> i2css -+ I2CSS_na_m = 0x00000020, -+ I2CSS_err_b = 6, // In I2C-> i2css -+ I2CSS_err_m = 0x00000040, -+ -+ I2CSSM_rr_b = 0, // In I2C-> i2cssm -+ I2CSSM_rr_m = 0x00000001, -+ I2CSSM_wr_b = 1, // In I2C-> i2cssm -+ I2CSSM_wr_m = 0x00000002, -+ I2CSSM_sa_b = 2, // In I2C-> i2cssm -+ I2CSSM_sa_m = 0x00000004, -+ I2CSSM_tf_b = 3, // In I2C-> i2cssm -+ I2CSSM_tf_m = 0x00000008, -+ I2CSSM_gc_b = 4, // In I2C-> i2cssm -+ I2CSSM_gc_m = 0x00000010, -+ I2CSSM_na_b = 5, // In I2C-> i2cssm -+ I2CSSM_na_m = 0x00000020, -+ I2CSSM_err_b = 6, // In I2C-> i2cssm -+ I2CSSM_err_m = 0x00000040, -+ -+ I2CSADDR_addr_b = 0, // In I2C-> i2csaddr -+ I2CSADDR_addr_m = 0x000003ff, -+ I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr -+ I2CSADDR_a_gc_m = 0x00000400, -+ I2CSADDR_a10_b = 11, // In I2C-> i2csaddr -+ I2CSADDR_a10_m = 0x00000800, -+ -+ I2CSACK_ack_b = 0, // In I2C-> i2csack -+ I2CSACK_ack_m = 0x00000001, -+ -+} ; -+#endif // __IDT_I2C_H__ -diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h ---- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/integ.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,78 @@ -+#ifndef __IDT_INTEG_H__ -+#define __IDT_INTEG_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * System Integrity register definition. -+ * -+ * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ -+ * -+ * Author : ryan.holmQVist@idt.com -+ * Date : 20011005 -+ * Update : -+ * $Log: integ.h,v $ -+ * Revision 1.3 2002/06/06 18:34:04 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.2 2002/06/05 18:32:33 astichte -+ * Removed IDTField -+ * -+ * Revision 1.1 2002/05/29 17:33:22 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ INTEG0_PhysicalAddress = 0x18030000, -+ INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default -+ -+ INTEG0_VirtualAddress = 0xb8030000, -+ INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default -+} ; -+ -+// if you are looing for CEA, try rst.h -+typedef struct -+{ -+ U32 filler [0xc] ; // 0x30 bytes unused. -+ U32 errcs ; // sticky use ERRCS_ -+ U32 wtcount ; // Watchdog timer count reg. -+ U32 wtcompare ; // Watchdog timer timeout value. -+ U32 wtc ; // Watchdog timer control. use WTC_ -+} volatile *INTEG_t ; -+ -+enum -+{ -+ ERRCS_wto_b = 0, // In INTEG_t -> errcs -+ ERRCS_wto_m = 0x00000001, -+ ERRCS_wne_b = 1, // In INTEG_t -> errcs -+ ERRCS_wne_m = 0x00000002, -+ ERRCS_ucw_b = 2, // In INTEG_t -> errcs -+ ERRCS_ucw_m = 0x00000004, -+ ERRCS_ucr_b = 3, // In INTEG_t -> errcs -+ ERRCS_ucr_m = 0x00000008, -+ ERRCS_upw_b = 4, // In INTEG_t -> errcs -+ ERRCS_upw_m = 0x00000010, -+ ERRCS_upr_b = 5, // In INTEG_t -> errcs -+ ERRCS_upr_m = 0x00000020, -+ ERRCS_udw_b = 6, // In INTEG_t -> errcs -+ ERRCS_udw_m = 0x00000040, -+ ERRCS_udr_b = 7, // In INTEG_t -> errcs -+ ERRCS_udr_m = 0x00000080, -+ ERRCS_sae_b = 8, // In INTEG_t -> errcs -+ ERRCS_sae_m = 0x00000100, -+ ERRCS_wre_b = 9, // In INTEG_t -> errcs -+ ERRCS_wre_m = 0x00000200, -+ -+ WTC_en_b = 0, // In INTEG_t -> wtc -+ WTC_en_m = 0x00000001, -+ WTC_to_b = 1, // In INTEG_t -> wtc -+ WTC_to_m = 0x00000002, -+} ; -+ -+#endif // __IDT_INTEG_H__ -diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h ---- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/int.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,167 @@ -+#ifndef __IDT_INT_H__ -+#define __IDT_INT_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Interrupt Controller register definition. -+ * -+ * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ -+ * -+ * Author : ryan.holmqvist@idt.com -+ * Date : 20011005 -+ * Update : -+ * $Log: int.h,v $ -+ * Revision 1.3 2002/06/06 18:34:04 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.2 2002/06/05 18:47:33 astichte -+ * Removed IDTField -+ * -+ * Revision 1.1 2002/05/29 17:33:22 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ INT0_PhysicalAddress = 0x18038000, -+ INT_PhysicalAddress = INT0_PhysicalAddress, // Default -+ -+ INT0_VirtualAddress = 0xb8038000, -+ INT_VirtualAddress = INT0_VirtualAddress, // Default -+} ; -+ -+struct INT_s -+{ -+ U32 ipend ; //Pending interrupts. use INT?_ -+ U32 itest ; //Test bits. use INT?_ -+ U32 imask ; //Interrupt disabled when set. use INT?_ -+} ; -+ -+enum -+{ -+ IPEND2 = 0, // HW 2 interrupt to core. use INT2_ -+ IPEND3 = 1, // HW 3 interrupt to core. use INT3_ -+ IPEND4 = 2, // HW 4 interrupt to core. use INT4_ -+ IPEND5 = 3, // HW 5 interrupt to core. use INT5_ -+ IPEND6 = 4, // HW 6 interrupt to core. use INT6_ -+ -+ IPEND_count, // must be last (used in loops) -+ IPEND_min = IPEND2 // min IPEND (used in loops) -+}; -+ -+typedef struct INTC_s -+{ -+ struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_ -+ U32 nmips ; // use NMIPS_ -+} volatile *INT_t ; -+ -+enum -+{ -+ INT2_timer0_b = 0, -+ INT2_timer0_m = 0x00000001, -+ INT2_timer1_b = 1, -+ INT2_timer1_m = 0x00000002, -+ INT2_timer2_b = 2, -+ INT2_timer2_m = 0x00000004, -+ INT2_refresh_b = 3, -+ INT2_refresh_m = 0x00000008, -+ INT2_watchdogTimeout_b = 4, -+ INT2_watchdogTimeout_m = 0x00000010, -+ INT2_undecodedCpuWrite_b = 5, -+ INT2_undecodedCpuWrite_m = 0x00000020, -+ INT2_undecodedCpuRead_b = 6, -+ INT2_undecodedCpuRead_m = 0x00000040, -+ INT2_undecodedPciWrite_b = 7, -+ INT2_undecodedPciWrite_m = 0x00000080, -+ INT2_undecodedPciRead_b = 8, -+ INT2_undecodedPciRead_m = 0x00000100, -+ INT2_undecodedDmaWrite_b = 9, -+ INT2_undecodedDmaWrite_m = 0x00000200, -+ INT2_undecodedDmaRead_b = 10, -+ INT2_undecodedDmaRead_m = 0x00000400, -+ INT2_ipBusSlaveAckError_b = 11, -+ INT2_ipBusSlaveAckError_m = 0x00000800, -+ -+ INT3_dmaChannel0_b = 0, -+ INT3_dmaChannel0_m = 0x00000001, -+ INT3_dmaChannel1_b = 1, -+ INT3_dmaChannel1_m = 0x00000002, -+ INT3_dmaChannel2_b = 2, -+ INT3_dmaChannel2_m = 0x00000004, -+ INT3_dmaChannel3_b = 3, -+ INT3_dmaChannel3_m = 0x00000008, -+ INT3_dmaChannel4_b = 4, -+ INT3_dmaChannel4_m = 0x00000010, -+ INT3_dmaChannel5_b = 5, -+ INT3_dmaChannel5_m = 0x00000020, -+ -+ INT5_uartGeneral0_b = 0, -+ INT5_uartGeneral0_m = 0x00000001, -+ INT5_uartTxrdy0_b = 1, -+ INT5_uartTxrdy0_m = 0x00000002, -+ INT5_uartRxrdy0_b = 2, -+ INT5_uartRxrdy0_m = 0x00000004, -+ INT5_pci_b = 3, -+ INT5_pci_m = 0x00000008, -+ INT5_pciDecoupled_b = 4, -+ INT5_pciDecoupled_m = 0x00000010, -+ INT5_spi_b = 5, -+ INT5_spi_m = 0x00000020, -+ INT5_deviceDecoupled_b = 6, -+ INT5_deviceDecoupled_m = 0x00000040, -+ INT5_i2cMaster_b = 7, -+ INT5_i2cMaster_m = 0x00000080, -+ INT5_i2cSlave_b = 8, -+ INT5_i2cSlave_m = 0x00000100, -+ INT5_ethOvr_b = 9, -+ INT5_ethOvr_m = 0x00000200, -+ INT5_ethUnd_b = 10, -+ INT5_ethUnd_m = 0x00000400, -+ INT5_ethPfd_b = 11, -+ INT5_ethPfd_m = 0x00000800, -+ INT5_nvram_b = 12, -+ INT5_nvram_m = 0x00001000, -+ -+ INT6_gpio0_b = 0, -+ INT6_gpio0_m = 0x00000001, -+ INT6_gpio1_b = 1, -+ INT6_gpio1_m = 0x00000002, -+ INT6_gpio2_b = 2, -+ INT6_gpio2_m = 0x00000004, -+ INT6_gpio3_b = 3, -+ INT6_gpio3_m = 0x00000008, -+ INT6_gpio4_b = 4, -+ INT6_gpio4_m = 0x00000010, -+ INT6_gpio5_b = 5, -+ INT6_gpio5_m = 0x00000020, -+ INT6_gpio6_b = 6, -+ INT6_gpio6_m = 0x00000040, -+ INT6_gpio7_b = 7, -+ INT6_gpio7_m = 0x00000080, -+ INT6_gpio8_b = 8, -+ INT6_gpio8_m = 0x00000100, -+ INT6_gpio9_b = 9, -+ INT6_gpio9_m = 0x00000200, -+ INT6_gpio10_b = 10, -+ INT6_gpio10_m = 0x00000400, -+ INT6_gpio11_b = 11, -+ INT6_gpio11_m = 0x00000800, -+ INT6_gpio12_b = 12, -+ INT6_gpio12_m = 0x00001000, -+ INT6_gpio13_b = 13, -+ INT6_gpio13_m = 0x00002000, -+ -+ NMIPS_gpio_b = 0, -+ NMIPS_gpio_m = 0x00000001, -+} ; -+ -+#endif // __IDT_INT_H__ -+ -+ -diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h ---- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,95 @@ -+#ifndef __IDT_IPARB_H__ -+#define __IDT_IPARB_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * IP Arbiter register definitions. -+ * -+ * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020120 -+ * Update : -+ * $Log: iparb.h,v $ -+ * Revision 1.3 2002/06/06 18:34:04 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.2 2002/06/05 19:01:42 astichte -+ * Removed IDTField -+ * -+ * Revision 1.1 2002/05/29 17:33:23 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ IPARB0_PhysicalAddress = 0x18048000, -+ IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default -+ -+ IPARB0_VirtualAddress = 0xb8048000, -+ IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default -+} ; -+ -+enum -+{ -+ IPABMXC_ethernetReceive = 0, -+ IPABMXC_ethernetTransmit = 1, -+ IPABMXC_memoryToHoldFifo = 2, -+ IPABMXC_holdFifoToMemory = 3, -+ IPABMXC_pciToMemory = 4, -+ IPABMXC_memoryToPci = 5, -+ IPABMXC_pciTarget = 6, -+ IPABMXC_pciTargetStart = 7, -+ IPABMXC_cpuToIpBus = 8, -+ -+ IPABMXC_Count, // Must be last in list ! -+ IPABMXC_Min = IPABMXC_ethernetReceive, -+ -+ IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest. -+} ; -+ -+typedef struct -+{ -+ U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_ -+ U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_ -+ U32 ipac ; // use IPAC_ -+ U32 ipaitcc; // use IPAITCC_ -+ U32 ipaspare ; -+} volatile * IPARB_t ; -+ -+enum -+{ -+ IPAC_dwm_b = 2, -+ IPAC_dwm_m = 0x00000004, -+ IPAC_drm_b = 3, -+ IPAC_drm_m = 0x00000008, -+ IPAC_msk_b = 4, -+ IPAC_msk_m = 0x00000010, -+ -+ IPAPC_ptc_b = 0, -+ IPAPC_ptc_m = 0x00003fff, -+ IPAPC_mf_b = 14, -+ IPAPC_mf_m = 0x00004000, -+ IPAPC_cptc_b = 16, -+ IPAPC_cptc_m = 0x3fff0000, -+ -+ IPAITCC_itcc = 0, -+ IPAITCC_itcc, = 0x000001ff, -+ -+ IPABMC_mtc_b = 0, -+ IPABMC_mtc_m = 0x00000fff, -+ IPABMC_p_b = 12, -+ IPABMC_p_m = 0x00003000, -+ IPABMC_msk_b = 14, -+ IPABMC_msk_m = 0x00004000, -+ IPABMC_cmtc_b = 16, -+ IPABMC_cmtc_m = 0x0fff0000, -+}; -+ -+#endif // __IDT_IPARB_H__ -diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h ---- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/irm.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,55 @@ -+#ifndef __IDT_IRM_H__ -+#define __IDT_IRM_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Internal Register Map -+ * -+ * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020605 -+ * Update : -+ * $Log: irm.h,v $ -+ * Revision 1.2 2002/06/05 14:51:06 astichte -+ * *** empty log message *** -+ * -+ * Revision 1.1 2002/05/29 17:33:23 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ ******************************************************************************/ -+ -+/* -+ * NOTE -- -+ * This file is here for backwards compatibility. -+ * DO NOT USE !!!! -+ */ -+ -+typedef enum -+{ -+ IRM_Physical = 0x18000000, // Internal Reg. map physical. -+ RST_Offset = 0x00000000, // Includes sysid and RST. -+ DEV_Offset = 0x00010000, // Device Controller 0. -+ DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller. -+ PMARB_Offset = 0x00020000, // PM bus arbiter. -+ TIM_Offset = 0x00028000, // Counter / timer. -+ INTEG_Offset = 0x00030000, // System Integrity. -+ INT_Offset = 0x00038000, // Interrupt controller. -+ DMA_Offset = 0x00040000, // DMA. -+ IPARB_Offset = 0x00044000, // IP bus arbiter. -+ GPIO_Offset = 0x00050000, // GPIO. -+ UART_Offset = 0x00058000, // UART -+ ETH_Offset = 0x00060000, // Ethernet 1. -+ I2C_Offset = 0x00068000, // I2C interface. -+ SPI_Offset = 0x00070000, // Serial Peripheral Interface. -+ NVRAM_Offset = 0x00078000, // NVRAM interface -+ AUTH_Offset = 0x0007c000, // Authorization unit -+ PCI_Offset = 0x00080000, -+ CROM_Offset = 0x000b8000, // Configuration ROM. -+ IRM_Size = 0x00200000, // Internal Reg. map size. -+} IRM_Offset_t ; -+ -+#endif // __IDT_IRM_H__ diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-12-14 04:09:50.000000000 +0100 @@ -3762,107 +2761,6 @@ diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc +#define NR_IRQS 256 + +#endif /* __ASM_MACH_MIPS_IRQ_H */ -diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h ---- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,97 @@ -+#ifndef __IDT_NVRAM_H -+#define __IDT_NVRAM_H -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * IP Arbiter register definitions. -+ * -+ * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $ -+ * -+ * Author : kiran.rao@idt.com -+ * Date : 20030724 -+ * Update : -+ * $Log: nvram.h,v $ -+ * -+ * -+ ******************************************************************************/ -+#include <asm/rc32434/tpes.h> -+ -+ -+enum -+{ -+ NVRAM0_PhysicalAddress = 0xba000000, -+ NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default -+ -+ NVRAM0_VirtualAddress = 0xba000000, -+ NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default -+} ; -+ -+enum -+{ -+ NVRCMD_cmd_b = 0, -+ NVRCMD_cmd_m = 0x0000007f, -+ -+ NVRS_r_b = 0, -+ NVRS_r_m = 0x00000001, -+ NVRS_e_b = 1, -+ NVRS_e_m = 0x00000002, -+ NVRS_k_b = 2, -+ NVRS_k_m = 0x00000004, -+ -+ NVRSM_r_b = 0, -+ NVRSM_r_m = 0x00000001, -+ NVRSM_e_b = 1, -+ NVRSM_e_m = 0x00000002, -+ NVRSM_k_b = 2, -+ NVRSM_k_m = 0x00000004, -+ -+ NVRCFG0_pwidth_b = 0, -+ NVRCFG0_pwidth_m = 0x00000003, -+ NVRCFG0_nmax_b = 2, -+ NVRCFG0_nmax_m = 0x0000000C, -+ NVRCFG0_vppl_b = 4, -+ NVRCFG0_vppl_m = 0x000000f0, -+ NVRCFG0_vppm_b = 8, -+ NVRCFG0_vppm_m = 0x00000300, -+ NVRCFG0_dvpp_b = 10, -+ NVRCFG0_dvpp_m = 0x00000c00, -+ NVRCFG0_x_b = 12, -+ NVRCFG0_x_m = 0x00007000, -+ -+ NVRCFG1_t1tecc_b = 0, -+ NVRCFG1_t1tecc_m = 0x00000003, -+ NVRCFG1_t1mrcl_b = 2, -+ NVRCFG1_t1mrcl_m = 0x0000000c, -+ NVRCFG1_t1bias_b = 4, -+ NVRCFG1_t1bias_m = 0x00000030, -+ NVRCFG1_t2tecc_b = 6, -+ NVRCFG1_t2tecc_m = 0x000000c0, -+ NVRCFG1_t2mrcl_b = 8, -+ NVRCFG1_t2mrcl_m = 0x00000300, -+ NVRCFG1_t2bias_b = 10, -+ NVRCFG1_t2bias_m = 0x00000c00, -+ NVRCFG1_t3tecc_b = 12, -+ NVRCFG1_t3tecc_m = 0x00003000, -+ NVRCFG1_t3mrcl_b = 14, -+ NVRCFG1_t3mrcl_m = 0x0000c000, -+ NVRCFG1_t3bias_b = 16, -+ NVRCFG1_t3bias_m = 0x00030000, -+ NVRCFG1_t4tecc_b = 18, -+ NVRCFG1_t4tecc_m = 0x000c0000, -+ NVRCFG1_t4mrcl_b = 20, -+ NVRCFG1_t4mrcl_m = 0x00300000, -+ NVRCFG1_t4bias_b = 22, -+ NVRCFG1_t4bias_m = 0x00c00000, -+ NVRCFG1_t5tecc_b = 24, -+ NVRCFG1_t5tecc_m = 0x03000000, -+ NVRCFG1_t5mrcl_b = 26, -+ NVRCFG1_t5mrcl_m = 0x0c000000, -+ NVRCFG1_t5bias_b = 28, -+ NVRCFG1_t5bias_m = 0x30000000, -+} -+ -+#endif // __IDT_NVRAM_H__ -+ diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-12-14 04:09:50.000000000 +0100 @@ -4562,236 +3460,12 @@ diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc + + + -diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h ---- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,209 @@ -+/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $ -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ */ -+#ifndef _PCIKORINA_H -+#define _PCIKORINA_H -+ -+ -+#define PCI_MSG_VirtualAddress 0xB8088010 -+#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress) -+#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress) -+ -+#define PCIM_SHFT 0x6 -+#define PCIM_BIT_LEN 0x7 -+#define PCIM_H_EA 0x3 -+#define PCIM_H_IA_FIX 0x4 -+#define PCIM_H_IA_RR 0x5 -+#if 0 -+#define PCI_ADDR_START 0x13000000 -+#endif -+ -+#define PCI_ADDR_START 0x50000000 -+ -+#define CPUTOPCI_MEM_WIN 0x02000000 -+#define CPUTOPCI_IO_WIN 0x00100000 -+#define PCILBA_SIZE_SHFT 2 -+#define PCILBA_SIZE_MASK 0x1F -+#define SIZE_256MB 0x1C -+#define SIZE_128MB 0x1B -+#define SIZE_64MB 0x1A -+#define SIZE_32MB 0x19 -+#define SIZE_16MB 0x18 -+#define SIZE_4MB 0x16 -+#define SIZE_2MB 0x15 -+#define SIZE_1MB 0x14 -+#define KORINA_CONFIG0_ADDR 0x80000000 -+#define KORINA_CONFIG1_ADDR 0x80000004 -+#define KORINA_CONFIG2_ADDR 0x80000008 -+#define KORINA_CONFIG3_ADDR 0x8000000C -+#define KORINA_CONFIG4_ADDR 0x80000010 -+#define KORINA_CONFIG5_ADDR 0x80000014 -+#define KORINA_CONFIG6_ADDR 0x80000018 -+#define KORINA_CONFIG7_ADDR 0x8000001C -+#define KORINA_CONFIG8_ADDR 0x80000020 -+#define KORINA_CONFIG9_ADDR 0x80000024 -+#define KORINA_CONFIG10_ADDR 0x80000028 -+#define KORINA_CONFIG11_ADDR 0x8000002C -+#define KORINA_CONFIG12_ADDR 0x80000030 -+#define KORINA_CONFIG13_ADDR 0x80000034 -+#define KORINA_CONFIG14_ADDR 0x80000038 -+#define KORINA_CONFIG15_ADDR 0x8000003C -+#define KORINA_CONFIG16_ADDR 0x80000040 -+#define KORINA_CONFIG17_ADDR 0x80000044 -+#define KORINA_CONFIG18_ADDR 0x80000048 -+#define KORINA_CONFIG19_ADDR 0x8000004C -+#define KORINA_CONFIG20_ADDR 0x80000050 -+#define KORINA_CONFIG21_ADDR 0x80000054 -+#define KORINA_CONFIG22_ADDR 0x80000058 -+#define KORINA_CONFIG23_ADDR 0x8000005C -+#define KORINA_CONFIG24_ADDR 0x80000060 -+#define KORINA_CONFIG25_ADDR 0x80000064 -+#define KORINA_CMD (PCFG04_command_ioena_m | \ -+ PCFG04_command_memena_m | \ -+ PCFG04_command_bmena_m | \ -+ PCFG04_command_mwinv_m | \ -+ PCFG04_command_parena_m | \ -+ PCFG04_command_serrena_m ) -+ -+#define KORINA_STAT (PCFG04_status_mdpe_m | \ -+ PCFG04_status_sta_m | \ -+ PCFG04_status_rta_m | \ -+ PCFG04_status_rma_m | \ -+ PCFG04_status_sse_m | \ -+ PCFG04_status_pe_m) -+ -+#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) -+ -+#define KORINA_REVID 0 -+#define KORINA_CLASS_CODE 0 -+#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \ -+ KORINA_REVID) -+ -+#define KORINA_CACHE_LINE_SIZE 4 -+#define KORINA_MASTER_LAT 0x3c -+#define KORINA_HEADER_TYPE 0 -+#define KORINA_BIST 0 -+ -+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \ -+ (KORINA_HEADER_TYPE<<16) | \ -+ (KORINA_MASTER_LAT<<8) | \ -+ KORINA_CACHE_LINE_SIZE ) -+ -+#define KORINA_BAR0 0x00000008 /* 128 MB Memory */ -+#define KORINA_BAR1 0x18800001 /* 1 MB IO */ -+#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia -+ internal Registers */ -+#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ -+ -+#define KORINA_CNFG4 KORINA_BAR0 -+#define KORINA_CNFG5 KORINA_BAR1 -+#define KORINA_CNFG6 KORINA_BAR2 -+#define KORINA_CNFG7 KORINA_BAR3 -+ -+#define KORINA_SUBSYS_VENDOR_ID 0 -+#define KORINA_SUBSYSTEM_ID 0 -+#define KORINA_CNFG8 0 -+#define KORINA_CNFG9 0 -+#define KORINA_CNFG10 0 -+#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ -+ KORINA_SUBSYSTEM_ID) -+#define KORINA_INT_LINE 1 -+#define KORINA_INT_PIN 1 -+#define KORINA_MIN_GNT 8 -+#define KORINA_MAX_LAT 0x38 -+#define KORINA_CNFG12 0 -+#define KORINA_CNFG13 0 -+#define KORINA_CNFG14 0 -+#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ -+ (KORINA_MIN_GNT<<16) | \ -+ (KORINA_INT_PIN<<8) | \ -+ KORINA_INT_LINE) -+#define KORINA_RETRY_LIMIT 0x80 -+#define KORINA_TRDY_LIMIT 0x80 -+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ -+ KORINA_TRDY_LIMIT) -+#define PCI_PBAxC_R 0x0 -+#define PCI_PBAxC_RL 0x1 -+#define PCI_PBAxC_RM 0x2 -+#define SIZE_SHFT 2 -+ -+#ifdef __MIPSEB__ -+#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \ -+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \ -+ PCIPBAC_pp_m | \ -+ (SIZE_32MB<<SIZE_SHFT) | \ -+ PCIPBAC_p_m) -+#else -+#define KORINA_PBA0C ( PCIPBAC_mrl_m | \ -+ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \ -+ PCIPBAC_pp_m | \ -+ (SIZE_32MB<<SIZE_SHFT) | \ -+ PCIPBAC_p_m) -+#endif -+ -+#if 0 -+ -+#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \ -+ ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \ -+ (SIZE_128MB<<SIZE_SHFT)) -+#endif -+#define KORINA_CNFG17 KORINA_PBA0C -+#define KORINA_PBA0M 0x0 -+#define KORINA_CNFG18 KORINA_PBA0M -+ -+#ifdef __MIPSEB__ -+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \ -+ PCIPBAC_msi_m) -+#else -+#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \ -+ PCIPBAC_msi_m) -+ -+#endif -+ -+#define KORINA_CNFG19 KORINA_PBA1C -+#define KORINA_PBA1M 0x0 -+#define KORINA_CNFG20 KORINA_PBA1M -+ -+#ifdef __MIPSEB__ -+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \ -+ PCIPBAC_msi_m) -+#else -+#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \ -+ PCIPBAC_msi_m) -+ -+#endif -+#define KORINA_CNFG21 KORINA_PBA2C -+#define KORINA_PBA2M 0x18000000 -+#define KORINA_CNFG22 KORINA_PBA2M -+#define KORINA_PBA3C 0 -+#define KORINA_CNFG23 KORINA_PBA3C -+#define KORINA_PBA3M 0 -+#define KORINA_CNFG24 KORINA_PBA3M -+ -+ -+ -+#define PCITC_DTIMER_VAL 8 -+#define PCITC_RTIMER_VAL 0x10 -+ -+ -+#endif /* _PCIKORINA_H */ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h ---- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,8 @@ -+/* Override the default address space for this arch -+*/ -+ -+#include <linux/pci_regs.h> -+ -+//#undef PCI_BASE_ADDRESS_SPACE -+//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY -+ diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-12-14 04:09:50.000000000 +0100 @@ -0,0 +1,84 @@ +/* ++ * Copyright (C) 2004 IDT Inc. + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify @@ -4804,7 +3478,6 @@ diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc3 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * -+ * $Id$ + */ +#ifndef __MIPS_RB_H__ +#define __MIPS_RB_H__ @@ -4878,7 +3551,7 @@ diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc3 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,126 @@ +@@ -0,0 +1,122 @@ +/* + *************************************************************************** + * Definitions for IDT RC323434 CPU. @@ -4909,14 +3582,13 @@ diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mip +#include <linux/autoconf.h> +#include <linux/delay.h> +#include <asm/io.h> -+#include <asm/rc32434/timer.h> + +#define RC32434_REG_BASE 0x18000000 + +#define interrupt ((volatile INT_t ) INT0_VirtualAddress) -+#define timer ((volatile TIM_t) TIM0_VirtualAddress) +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress) + ++ +#define IDT_CLOCK_MULT 2 +#define MIPS_CPU_TIMER_IRQ 7 +/* Interrupt Controller */ @@ -5001,618 +3673,5 @@ diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mip + return ret; +} + -+extern void cons_putc(char c); -+extern void cons_puts(char *s); -+ +#endif /* _RC32434_H_ */ -diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h ---- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/rst.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,105 @@ -+#ifndef __IDT_RST_H__ -+#define __IDT_RST_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Reset register definitions. -+ * -+ * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020118 -+ * Update : -+ * $Log: rst.h,v $ -+ * Revision 1.2 2002/06/06 18:34:05 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.1 2002/05/29 17:33:24 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ RST0_PhysicalAddress = 0x18000000, -+ RST_PhysicalAddress = RST0_PhysicalAddress, // Default -+ -+ RST0_VirtualAddress = 0xb8000000, -+ RST_VirtualAddress = RST0_VirtualAddress, // Default -+} ; -+ -+typedef struct RST_s -+{ -+ U32 filler [0x0006] ; -+ U32 sysid ; -+ U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000 -+ U32 reset ; -+ U32 bcv ; -+ U32 cea ; -+} volatile * RST_t ; -+ -+enum -+{ -+ SYSID_rev_b = 0, -+ SYSID_rev_m = 0x000000ff, -+ SYSID_imp_b = 8, -+ SYSID_imp_m = 0x000fff00, -+ SYSID_vendor_b = 20, -+ SYSID_vendor_m = 0xfff00000, -+ -+ BCV_pll_b = 0, -+ BCV_pll_m = 0x0000000f, -+ BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK. -+ BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK. -+ BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK. -+ BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK. -+ BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK. -+ BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK. -+ BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK. -+ BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK. -+ BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK. -+ BCV_pll_Res5_v = 0x9, -+ BCV_pll_Res6_v = 0xa, -+ BCV_pll_Res7_v = 0xb, -+ BCV_pll_Res8_v = 0xc, -+ BCV_pll_Res13_v = 0xd, -+ BCV_pll_Res14_v = 0xe, -+ BCV_pll_Res15_v = 0xf, -+ BCV_clkDiv_b = 4, -+ BCV_clkDiv_m = 0x00000030, -+ BCV_clkDiv_Div1_v = 0x0, -+ BCV_clkDiv_Div2_v = 0x1, -+ BCV_clkDiv_Div4_v = 0x2, -+ BCV_clkDiv_Res3_v = 0x3, -+ BCV_bigEndian_b = 6, -+ BCV_bigEndian_m = 0x00000040, -+ BCV_resetFast_b = 7, -+ BCV_resetFast_m = 0x00000080, -+ BCV_pciMode_b = 8, -+ BCV_pciMode_m = 0x00000100, -+ BCV_pciMode_disabled_v = 0, // PCI is disabled. -+ BCV_pciMode_tnr_v = 1, // satellite Target Not Ready. -+ BCV_pciMode_suspended_v = 2, // satellite with suspended CPU. -+ BCV_pciMode_external_v = 3, // host, external arbiter. -+ BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter. -+ BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter. -+ BCV_pciMode_res6_v = 6, -+ BCV_pciMode_res7_v = 7, -+ BCV_watchDisable_b = 11, -+ BCV_watchDisable_m = 0x00000800, -+ BCV_pllTest_b = 12, -+ BCV_pllTest_m = 0x00001000, -+ BCV_nvramInit_b = 13, -+ BCV_nvramInit_m = 0x00002000, -+ BCV_clksyncTstMd_b = 14, -+ BCV_clksyncTstMd_m = 0x00004000, -+ BCV_delayBypass_b = 15, -+ BCV_delayByPass_m = 0x00008000, -+} ; -+#endif // __IDT_RST_H__ -diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h ---- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/spi.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,100 @@ -+#ifndef __IDT_SPI_H__ -+#define __IDT_SPI_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Serial Peripheral Interface register definitions. -+ * -+ * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $ -+ * -+ * Author : ryan.holmQVist@idt.com -+ * Date : 20011005 -+ * Update : -+ * $Log: spi.h,v $ -+ * Revision 1.2 2002/06/06 18:34:05 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.1 2002/05/29 17:33:25 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ SPI0_PhysicalAddress = 0x18070000, -+ SPI_PhysicalAddress = SPI0_PhysicalAddress, -+ -+ SPI0_VirtualAddress = 0xb8070000, -+ SPI_VirtualAddress = SPI0_VirtualAddress, -+} ; -+ -+typedef struct -+{ -+ U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR) -+ U32 spc ; // spi control reg use SPC_ -+ U32 sps ; // spi status reg use SPS_ -+ U32 spd ; // spi data reg use SPD_ -+ U32 siofunc ; // serial IO function use SIOFUNC_ -+ U32 siocfg ; // serial IO config use SIOCFG_ -+ U32 siod; // serial IO data use SIOD_ -+} volatile *SPI_t ; -+ -+enum -+{ -+ SPCP_div_b = 0, -+ SPCP_div_m = 0x000000ff, -+ SPC_spr_b = 0, -+ SPC_spr_m = 0x00000003, -+ SPC_spr_div2_v = 0, -+ SPC_spr_div4_v = 1, -+ SPC_spr_div16_v = 2, -+ SPC_spr_div32_v = 3, -+ SPC_cpha_b = 2, -+ SPC_cpha_m = 0x00000004, -+ SPC_cpol_b = 3, -+ SPC_cpol_m = 0x00000008, -+ SPC_mstr_b = 4, -+ SPC_mstr_m = 0x00000010, -+ SPC_spe_b = 6, -+ SPC_spe_m = 0x00000040, -+ SPC_spie_b = 7, -+ SPC_spie_m = 0x00000080, -+ -+ SPS_modf_b = 4, -+ SPS_modf_m = 0x00000010, -+ SPS_wcol_b = 6, -+ SPS_wcol_m = 0x00000040, -+ SPS_spif_b = 7, -+ SPS_spif_m = 0x00000070, -+ -+ SPD_data_b = 0, -+ SPD_data_m = 0x000000ff, -+ -+ SIOFUNC_sdo_b = 0, -+ SIOFUNC_sdo_m = 0x00000001, -+ SIOFUNC_sdi_b = 1, -+ SIOFUNC_sdi_m = 0x00000002, -+ SIOFUNC_sck_b = 2, -+ SIOFUNC_sck_m = 0x00000004, -+ -+ SIOCFG_sdo_b = 0, -+ SIOCFG_sdo_m = 0x00000001, -+ SIOCFG_sdi_b = 1, -+ SIOCFG_sdi_m = 0x00000002, -+ SIOCFG_sck_b = 2, -+ SIOCFG_sck_m = 0x00000004, -+ -+ SIOD_sdo_b = 0, -+ SIOD_sdo_m = 0x00000001, -+ SIOD_sdi_b = 1, -+ SIOD_sdi_m = 0x00000002, -+ SIOD_sck_b = 2, -+ SIOD_sck_m = 0x00000004, -+} ; -+#endif // __IDT_SPI_H__ -diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h ---- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/timer.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,91 @@ -+/************************************************************************** -+ * -+ * BRIEF MODULE DESCRIPTION -+ * Definitions for timer registers -+ * -+ * Copyright 2004 IDT Inc. (rischelp@idt.com) -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * -+ ************************************************************************** -+ * May 2004 rkt,neb. -+ * -+ * Initial Release -+ * -+ * -+ * -+ ************************************************************************** -+ */ -+ -+#ifndef __IDT_TIM_H__ -+#define __IDT_TIM_H__ -+ -+enum -+{ -+ TIM0_PhysicalAddress = 0x18028000, -+ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default -+ -+ TIM0_VirtualAddress = 0xb8028000, -+ TIM_VirtualAddress = TIM0_VirtualAddress, // Default -+} ; -+ -+enum -+{ -+ TIM_Count = 3, -+} ; -+ -+struct TIM_CNTR_s -+{ -+ u32 count ; -+ u32 compare ; -+ u32 ctc ; //use CTC_ -+} ; -+ -+typedef struct TIM_s -+{ -+ struct TIM_CNTR_s tim [TIM_Count] ; -+ u32 rcount ; //use RCOUNT_ -+ u32 rcompare ; //use RCOMPARE_ -+ u32 rtc ; //use RTC_ -+} volatile * TIM_t ; -+ -+enum -+{ -+ CTC_en_b = 0, -+ CTC_en_m = 0x00000001, -+ CTC_to_b = 1, -+ CTC_to_m = 0x00000002, -+ -+ RCOUNT_count_b = 0, -+ RCOUNT_count_m = 0x0000ffff, -+ RCOMPARE_compare_b = 0, -+ RCOMPARE_compare_m = 0x0000ffff, -+ RTC_ce_b = 0, -+ RTC_ce_m = 0x00000001, -+ RTC_to_b = 1, -+ RTC_to_m = 0x00000002, -+ RTC_rqe_b = 2, -+ RTC_rqe_m = 0x00000004, -+ -+} ; -+#endif // __IDT_TIM_H__ -+ -diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h ---- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/tim.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,78 @@ -+#ifndef __IDT_TIM_H__ -+#define __IDT_TIM_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Timer register definition. -+ * -+ * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $ -+ * -+ * Author : ryan.holmQVist@idt.com -+ * Date : 20011005 -+ * Update : -+ * $Log: tim.h,v $ -+ * Revision 1.2 2002/06/06 18:34:05 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.1 2002/05/29 17:33:25 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ TIM0_PhysicalAddress = 0x18028000, -+ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default -+ -+ TIM0_VirtualAddress = 0xb8028000, -+ TIM_VirtualAddress = TIM0_VirtualAddress, // Default -+} ; -+ -+enum -+{ -+ TIM_Count = 3, -+} ; -+ -+struct TIM_CNTR_s -+{ -+ U32 count ; -+ U32 compare ; -+ U32 ctc ; //use CTC_ -+} ; -+ -+typedef struct TIM_s -+{ -+ struct TIM_CNTR_s tim [TIM_Count] ; -+ U32 rcount ; //use RCOUNT_ -+ U32 rcompare ; //use RCOMPARE_ -+ U32 rtc ; //use RTC_ -+} volatile * TIM_t ; -+ -+enum -+{ -+ CTC_en_b = 0, -+ CTC_en_m = 0x00000001, -+ CTC_to_b = 1, -+ CTC_to_m = 0x00000002, -+ -+ RCOUNT_count_b = 0, -+ RCOUNT_count_m = 0x0000ffff, -+ RCOMPARE_compare_b = 0, -+ RCOMPARE_compare_m = 0x0000ffff, -+ RTC_ce_b = 0, -+ RTC_ce_m = 0x00000001, -+ RTC_to_b = 1, -+ RTC_to_m = 0x00000002, -+ RTC_rqe_b = 2, -+ RTC_rqe_m = 0x00000004, -+ -+} ; -+#endif // __IDT_TIM_H__ -+ -diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h ---- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/types.h 2006-12-14 04:10:43.000000000 +0100 -@@ -0,0 +1,35 @@ -+#ifndef __IDT_TYPES_H__ -+#define __IDT_TYPES_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * Common typedefs used in IDT-generated code. -+ * -+ * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020606 -+ * Update : -+ * $Log: types.h,v $ -+ * Revision 1.1 2002/06/06 16:16:56 astichte -+ * Added -+ * -+ * -+ ******************************************************************************/ -+ -+typedef unsigned char U8 ; -+typedef signed char S8 ; -+ -+typedef unsigned short U16 ; -+typedef signed short S16 ; -+ -+typedef unsigned int U32 ; -+typedef signed int S32 ; -+ -+typedef unsigned long long U64 ; -+typedef signed long long S64 ; -+ -+#endif // __IDT_TYPES_H__ -diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h ---- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/rc32434/uart.h 2006-12-14 04:09:50.000000000 +0100 -@@ -0,0 +1,178 @@ -+#ifndef __IDT_UART_H__ -+#define __IDT_UART_H__ -+ -+/******************************************************************************* -+ * -+ * Copyright 2002 Integrated Device Technology, Inc. -+ * All rights reserved. -+ * -+ * UART register definitions. -+ * -+ * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $ -+ * -+ * Author : Allen.Stichter@idt.com -+ * Date : 20020118 -+ * Update : -+ * $Log: uart.h,v $ -+ * Revision 1.3 2002/06/06 18:34:05 astichte -+ * Added XXX_PhysicalAddress and XXX_VirtualAddress -+ * -+ * Revision 1.2 2002/06/04 17:37:52 astichte -+ * Updated register definitions. -+ * -+ * Revision 1.1 2002/05/29 17:33:25 sysarch -+ * jba File moved from vcode/include/idt/acacia -+ * -+ * -+ ******************************************************************************/ -+ -+#include <asm/rc32434/types.h> -+ -+enum -+{ -+ UART_PhysicalAddress = 0x18058000, -+ UART_PhysicalAddress = UART_PhysicalAddress, // Default -+ -+ UART_VirtualAddress = 0xb8058000, -+ UART_VirtualAddress = UART_VirtualAddress, // Default -+} ; -+ -+/* -+ * Register definitions are in bytes so we can handle endian problems. -+ */ -+ -+typedef struct UART_s -+{ -+ union -+ { -+ U32 const uartrb ; // 0x00 - DLAB=0, read. -+ U32 uartth ; // 0x00 - DLAB=0, write. -+ U32 uartdll ; // 0x00 - DLAB=1, read/write. -+ } ; -+ -+ union -+ { -+ U32 uartie ; // 0x04 - DLAB=0, read/write. -+ U32 uartdlh ; // 0x04 - DLAB=1, read/write. -+ } ; -+ union -+ { -+ U32 const uartii ; // 0x08 - DLAB=0, read. -+ U32 uartfc ; // 0x08 - DLAB=0, write. -+ } ; -+ -+ U32 uartlc ; // 0x0c -+ U32 uartmc ; // 0x10 -+ U32 uartls ; // 0x14 -+ U32 uartms ; // 0x18 -+ U32 uarts ; // 0x1c -+} volatile *UART_t ; -+ -+// Reset registers. -+typedef U32 volatile *UARTRR_t ; -+ -+enum -+{ -+ UARTIE_rda_b = 0, -+ UARTIE_rda_m = 0x00000001, -+ UARTIE_the_b = 1, -+ UARTIE_the_m = 0x00000002, -+ UARTIE_rls_b = 2, -+ UARTIE_rls_m = 0x00000004, -+ UARTIE_ems_b = 3, -+ UARTIE_ems_m = 0x00000008, -+ -+ UARTII_pi_b = 0, -+ UARTII_pi_m = 0x00000001, -+ UARTII_iid_b = 1, -+ UARTII_iid_m = 0x0000000e, -+ UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD. -+ UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty. -+ UARTII_iid_rda_v = 2, // Receive data available -+ UARTII_iid_rls_v = 3, // Overrun, parity, etc, error. -+ UARTII_iid_res4_v = 4, // reserved. -+ UARTII_iid_res5_v = 5, // reserved. -+ UARTII_iid_cto_v = 6, // Character timeout. -+ UARTII_iid_res7_v = 7, // reserved. -+ -+ UARTFC_en_b = 0, -+ UARTFC_en_m = 0x00000001, -+ UARTFC_rr_b = 1, -+ UARTFC_rr_m = 0x00000002, -+ UARTFC_tr_b = 2, -+ UARTFC_tr_m = 0x00000004, -+ UARTFC_dms_b = 3, -+ UARTFC_dms_m = 0x00000008, -+ UARTFC_rt_b = 6, -+ UARTFC_rt_m = 0x000000c0, -+ UARTFC_rt_1Byte_v = 0, -+ UARTFC_rt_4Byte_v = 1, -+ UARTFC_rt_8Byte_v = 2, -+ UARTFC_rt_14Byte_v = 3, -+ -+ UARTLC_wls_b = 0, -+ UARTLC_wls_m = 0x00000003, -+ UARTLC_wls_5Bits_v = 0, -+ UARTLC_wls_6Bits_v = 1, -+ UARTLC_wls_7Bits_v = 2, -+ UARTLC_wls_8Bits_v = 3, -+ UARTLC_stb_b = 2, -+ UARTLC_stb_m = 0x00000004, -+ UARTLC_pen_b = 3, -+ UARTLC_pen_m = 0x00000008, -+ UARTLC_eps_b = 4, -+ UARTLC_eps_m = 0x00000010, -+ UARTLC_sp_b = 5, -+ UARTLC_sp_m = 0x00000020, -+ UARTLC_sb_b = 6, -+ UARTLC_sb_m = 0x00000040, -+ UARTLC_dlab_b = 7, -+ UARTLC_dlab_m = 0x00000080, -+ -+ UARTMC_dtr_b = 0, -+ UARTMC_dtr_m = 0x00000001, -+ UARTMC_rts_b = 1, -+ UARTMC_rts_m = 0x00000002, -+ UARTMC_o1_b = 2, -+ UARTMC_o1_m = 0x00000004, -+ UARTMC_o2_b = 3, -+ UARTMC_o2_m = 0x00000008, -+ UARTMC_lp_b = 4, -+ UARTMC_lp_m = 0x00000010, -+ -+ UARTLS_dr_b = 0, -+ UARTLS_dr_m = 0x00000001, -+ UARTLS_oe_b = 1, -+ UARTLS_oe_m = 0x00000002, -+ UARTLS_pe_b = 2, -+ UARTLS_pe_m = 0x00000004, -+ UARTLS_fe_b = 3, -+ UARTLS_fe_m = 0x00000008, -+ UARTLS_bi_b = 4, -+ UARTLS_bi_m = 0x00000010, -+ UARTLS_thr_b = 5, -+ UARTLS_thr_m = 0x00000020, -+ UARTLS_te_b = 6, -+ UARTLS_te_m = 0x00000040, -+ UARTLS_rfe_b = 7, -+ UARTLS_rfe_m = 0x00000080, -+ -+ UARTMS_dcts_b = 0, -+ UARTMS_dcts_m = 0x00000001, -+ UARTMS_ddsr_b = 1, -+ UARTMS_ddsr_m = 0x00000002, -+ UARTMS_teri_b = 2, -+ UARTMS_teri_m = 0x00000004, -+ UARTMS_ddcd_b = 3, -+ UARTMS_ddcd_m = 0x00000008, -+ UARTMS_cts_b = 4, -+ UARTMS_cts_m = 0x00000010, -+ UARTMS_dsr_b = 5, -+ UARTMS_dsr_m = 0x00000020, -+ UARTMS_ri_b = 6, -+ UARTMS_ri_m = 0x00000040, -+ UARTMS_dcd_b = 7, -+ UARTMS_dcd_m = 0x00000080, -+} ; -+ -+#endif // __IDT_UART_H__ + |