diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2021-05-15 16:21:46 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2021-05-15 19:32:20 +0200 |
| commit | 9d21eccc6b763a1e2f0a0ed0bcb4561ea0ed68ff (patch) | |
| tree | 583c92bf887bbd32e6a2ebfae54d888ceb7ba556 /target/linux/ramips | |
| parent | c287500a656e43da45b203fb3c4463d9089c5986 (diff) | |
| download | upstream-9d21eccc6b763a1e2f0a0ed0bcb4561ea0ed68ff.tar.gz upstream-9d21eccc6b763a1e2f0a0ed0bcb4561ea0ed68ff.tar.bz2 upstream-9d21eccc6b763a1e2f0a0ed0bcb4561ea0ed68ff.zip | |
kernel: bump 5.4 to 5.4.119
Removed because in upstream
generic/backport-5.4/050-gro-fix-napi_gro_frags-Fast-GRO-breakage-due-to-IP-a.patch
ath79/patches-5.4/0050-spi-ath79-remove-spi-master-setup-and-cleanup-assign.patch
ramips/patches-5.4/999-fix-pci-init-mt7620.patch
Manually rebased
ath79/patches-5.4/0033-spi-ath79-drop-pdata-support.patch
All others updated automatically.
Compile-tested on: x86/64, ath79/generic
Runtime-tested on: x86/64, ath79/generic
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/ramips')
| -rw-r--r-- | target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch deleted file mode 100644 index 7c00d4c9ae..0000000000 --- a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/mips/pci/pci-mt7620.c -+++ b/arch/mips/pci/pci-mt7620.c -@@ -32,6 +32,7 @@ - #define PPLL_CFG1 0x9c - - #define PPLL_DRV 0xa0 -+#define PPLL_LD BIT(23) - #define PDRV_SW_SET BIT(31) - #define LC_CKDRVPD BIT(19) - #define LC_CKDRVOHZ BIT(18) -@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla - rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); - mdelay(100); - -- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) { -- dev_err(&pdev->dev, "MT7620 PPLL unlock\n"); -+ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { -+ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n"); - reset_control_assert(rstpcie0); - rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); - return -1; |