aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ramips
diff options
context:
space:
mode:
authorJohn Crispin <john@phrozen.org>2016-07-06 21:42:54 +0200
committerJohn Crispin <john@phrozen.org>2016-07-11 14:19:46 +0200
commit252f7516119d4c7ab448dfc91c902d5703c823eb (patch)
treefd745e4ab0c08fe93e0c9a22fbf70ef0fded9e75 /target/linux/ramips
parent09907170ddf8fc50ff14f8d8715c438f1721cc9c (diff)
downloadupstream-252f7516119d4c7ab448dfc91c902d5703c823eb.tar.gz
upstream-252f7516119d4c7ab448dfc91c902d5703c823eb.tar.bz2
upstream-252f7516119d4c7ab448dfc91c902d5703c823eb.zip
ramips: fix usb phy initialisation
this broke usb20 device detection. Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ramips')
-rw-r--r--target/linux/ramips/dts/mt7628an.dtsi2
-rw-r--r--target/linux/ramips/patches-4.4/0086-usbphy.patch35
2 files changed, 36 insertions, 1 deletions
diff --git a/target/linux/ramips/dts/mt7628an.dtsi b/target/linux/ramips/dts/mt7628an.dtsi
index 671aaef386..dc3ba9e323 100644
--- a/target/linux/ramips/dts/mt7628an.dtsi
+++ b/target/linux/ramips/dts/mt7628an.dtsi
@@ -360,7 +360,7 @@
usbphy: usbphy@10120000 {
compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
- reg = <0x10120000 0x4000>;
+ reg = <0x10120000 0x1000>;
#phy-cells = <1>;
resets = <&rstctrl 22 &rstctrl 25>;
diff --git a/target/linux/ramips/patches-4.4/0086-usbphy.patch b/target/linux/ramips/patches-4.4/0086-usbphy.patch
new file mode 100644
index 0000000000..92265e6a5d
--- /dev/null
+++ b/target/linux/ramips/patches-4.4/0086-usbphy.patch
@@ -0,0 +1,35 @@
+--- a/drivers/phy/phy-ralink-usb.c
++++ b/drivers/phy/phy-ralink-usb.c
+@@ -34,19 +34,19 @@
+ #define RT_SYSC_REG_CLKCFG1 0x030
+ #define RT_SYSC_REG_USB_PHY_CFG 0x05c
+
+-#define OFS_U2_PHY_AC0 0x00
+-#define OFS_U2_PHY_AC1 0x04
+-#define OFS_U2_PHY_AC2 0x08
+-#define OFS_U2_PHY_ACR0 0x10
+-#define OFS_U2_PHY_ACR1 0x14
+-#define OFS_U2_PHY_ACR2 0x18
+-#define OFS_U2_PHY_ACR3 0x1C
+-#define OFS_U2_PHY_ACR4 0x20
+-#define OFS_U2_PHY_AMON0 0x24
+-#define OFS_U2_PHY_DCR0 0x60
+-#define OFS_U2_PHY_DCR1 0x64
+-#define OFS_U2_PHY_DTM0 0x68
+-#define OFS_U2_PHY_DTM1 0x6C
++#define OFS_U2_PHY_AC0 0x800
++#define OFS_U2_PHY_AC1 0x804
++#define OFS_U2_PHY_AC2 0x808
++#define OFS_U2_PHY_ACR0 0x810
++#define OFS_U2_PHY_ACR1 0x814
++#define OFS_U2_PHY_ACR2 0x818
++#define OFS_U2_PHY_ACR3 0x81C
++#define OFS_U2_PHY_ACR4 0x820
++#define OFS_U2_PHY_AMON0 0x824
++#define OFS_U2_PHY_DCR0 0x860
++#define OFS_U2_PHY_DCR1 0x864
++#define OFS_U2_PHY_DTM0 0x868
++#define OFS_U2_PHY_DTM1 0x86C
+
+ #define RT_RSTCTRL_UDEV BIT(25)
+ #define RT_RSTCTRL_UHST BIT(22)