diff options
author | John Crispin <blogic@openwrt.org> | 2014-11-14 16:52:52 +0000 |
---|---|---|
committer | John Crispin <blogic@openwrt.org> | 2014-11-14 16:52:52 +0000 |
commit | 170c9f6bb62b27861b061d626bc503f3051bd410 (patch) | |
tree | fca66c636c24432344baeac0697a9a542b6065fc /target/linux/ramips | |
parent | 29830538135c8f2d8524c2b0c70ed176c3a2c1b3 (diff) | |
download | upstream-170c9f6bb62b27861b061d626bc503f3051bd410.tar.gz upstream-170c9f6bb62b27861b061d626bc503f3051bd410.tar.bz2 upstream-170c9f6bb62b27861b061d626bc503f3051bd410.zip |
ralink: update ethernet driver to use new ralink_soc variable
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@43247 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips')
-rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c | 32 | ||||
-rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c | 17 |
2 files changed, 7 insertions, 42 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c index ae37a0307d..247983b79e 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3052.c @@ -38,28 +38,6 @@ #include <linux/mii.h> #include <ralink_regs.h> -#ifdef CONFIG_SOC_MT7620 -static inline int soc_is_rt3352(void) -{ - return 0; -} - -static inline int soc_is_mt7628(void) -{ - return 1; -} - -static inline int soc_is_rt5350(void) -{ - return 0; -} -#else -#include <asm/mach-ralink/rt305x.h> -static inline int soc_is_mt7628(void) -{ - return 0; -} -#endif #include <asm/mach-ralink/rt305x_esw_platform.h> @@ -532,7 +510,7 @@ static void esw_hw_init(struct rt305x_esw *esw) for (i = 0; i < 6; i++) esw->ports[i].disable = (port_disable & (1 << i)) != 0; - if (soc_is_rt3352()) { + if (ralink_soc == RT305X_SOC_RT3352) { /* reset EPHY */ u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); @@ -583,7 +561,7 @@ static void esw_hw_init(struct rt305x_esw *esw) rt305x_mii_write(esw, 0, 29, 0x598b); /* select local register */ rt305x_mii_write(esw, 0, 31, 0x8000); - } else if (soc_is_rt5350()) { + } else if (ralink_soc == RT305X_SOC_RT5350) { /* reset EPHY */ u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL); @@ -638,9 +616,9 @@ static void esw_hw_init(struct rt305x_esw *esw) rt305x_mii_write(esw, 0, 29, 0x598b); /* select local register */ rt305x_mii_write(esw, 0, 31, 0x8000); - } else if (soc_is_mt7628()) { + } else if (ralink_soc == MT762X_SOC_MT7628AN) { int i; - u32 phy_val; +// u32 phy_val; u32 val; /* reset EPHY */ @@ -1071,7 +1049,7 @@ esw_get_port_tr_badgood(struct switch_dev *dev, int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16; u32 reg; - if (!soc_is_rt5350() && !soc_is_mt7628()) + if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN)) return -EINVAL; if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c index c406013228..1ece54855c 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt305x.c @@ -18,19 +18,6 @@ #include <linux/module.h> #include <asm/mach-ralink/ralink_regs.h> -#ifdef CONFIG_SOC_MT7620 -static inline int soc_is_rt3352(void) -{ - return 0; -} - -static inline int soc_is_rt3052(void) -{ - return 0; -} -#else -#include <asm/mach-ralink/rt305x.h> -#endif #include "ralink_soc_eth.h" #include "mdio_rt2880.h" @@ -69,14 +56,14 @@ static int rt3050_fwd_config(struct fe_priv *priv) { int ret; - if (soc_is_rt3052()) { + if (ralink_soc != RT305X_SOC_RT3052) { ret = fe_set_clock_cycle(priv); if (ret) return ret; } fe_fwd_config(priv); - if (!soc_is_rt3352()) + if (ralink_soc != RT305X_SOC_RT3352) fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG); fe_csum_config(priv); |