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authorGabor Juhos <juhosg@openwrt.org>2009-09-01 19:34:24 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-09-01 19:34:24 +0000
commit101f70750576fac1e04117a9d0dcb3397e8709e2 (patch)
tree9c32c030bfcfbd7a491fb5ee3ca2bb977a39bef3 /target/linux/ramips
parent5de1482bc71ed09aaf7ad7f5ccb4e7d61deac81e (diff)
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[ramips] cache_line_size is 16 on rt288x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17462 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips')
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h56
-rw-r--r--target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h (renamed from target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h)2
-rw-r--r--target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch9
3 files changed, 66 insertions, 1 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
new file mode 100644
index 0000000000..5e27363324
--- /dev/null
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/*
+ * Ralink RT288x specific CPU feature overrides
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This file was derived from: include/asm-mips/cpu-features.h
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_sb1_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+
+#define cpu_has_prefetch 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+
+#define cpu_has_mips16 1
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 1
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
+#define cpu_dcache_line_size() 16
+#define cpu_icache_line_size() 16
+
+#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
index 6c41da851f..3295d1a556 100644
--- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/cpu-feature-overrides.h
+++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
@@ -1,5 +1,5 @@
/*
- * Ralink RT288x/RT305x specific CPU feature overrides
+ * Ralink RT305x specific CPU feature overrides
*
* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
diff --git a/target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch b/target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch
index 42fd6ec5b8..1613cf43a5 100644
--- a/target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch
+++ b/target/linux/ramips/patches-2.6.30/100-mips-ralink-core.patch
@@ -47,3 +47,12 @@
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
+@@ -988,7 +992,7 @@
+
+ config MIPS_L1_CACHE_SHIFT
+ int
+- default "4" if MACH_DECSTATION || MIKROTIK_RB532
++ default "4" if MACH_DECSTATION || MIKROTIK_RB532 || RALINK_RT288X
+ default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
+ default "4" if PMC_MSP4200_EVAL
+ default "5"