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authorJohn Audia <graysky@archlinux.us>2021-05-14 05:05:17 -0400
committerHauke Mehrtens <hauke@hauke-m.de>2021-05-23 15:09:06 +0200
commit08593db128c4472225a7ffd58e21f06390d9c3f0 (patch)
treecb16b71fb6edd9b33f07d6d980dc6c553be85dff /target/linux/ramips/patches-5.4
parent3e1c92f9e1be108df2042ab211cc8d68938e6af9 (diff)
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kernel: bump 5.4 to 5.4.119
Removed upstreamed: generic/backport-5.4/050-gro-fix-napi_gro_frags-Fast-GRO-breakage-due-to-IP-a.patch bcm63xx/patches-5.4/434-nand-brcmnand-fix-OOB-R-W-with-Hamming-ECC.patch* Removed/code was included upstream and therefore redundant: ramips/patches-5.4/999-fix-pci-init-mt7620.patch All other patches automatically rebased. * update_kernel.sh did not flag this yet it was included in 5.4.119[1], as a result of the rebase, I removed my testing lines since I did not go back to test built or to run test 5.4.119 with the removed patch present. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.4.119&id=e5b3e69eb36ac1178a7a2392616fd29afd288c4e Signed-off-by: John Audia <graysky@archlinux.us>
Diffstat (limited to 'target/linux/ramips/patches-5.4')
-rw-r--r--target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch21
1 files changed, 0 insertions, 21 deletions
diff --git a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
deleted file mode 100644
index 7c00d4c9ae..0000000000
--- a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -32,6 +32,7 @@
- #define PPLL_CFG1 0x9c
-
- #define PPLL_DRV 0xa0
-+#define PPLL_LD BIT(23)
- #define PDRV_SW_SET BIT(31)
- #define LC_CKDRVPD BIT(19)
- #define LC_CKDRVOHZ BIT(18)
-@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla
- rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
- mdelay(100);
-
-- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
-- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
-+ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
-+ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
- reset_control_assert(rstpcie0);
- rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
- return -1;