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authorDENG Qingfang <dengqf6@mail2.sysu.edu.cn>2020-03-01 17:01:09 +0800
committerChuanhong Guo <gch981213@gmail.com>2020-04-04 12:04:13 +0800
commitc70545f397187b36c1220ae16b4db19f39857c93 (patch)
tree752dc048ea32cf02d8cba30fc54d024ed58ce812 /target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
parentb51ea43f900191bc8ce7411dad39239fac6df4f8 (diff)
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ramips: copy patches and kernel config to 5.4
Copy patches and kernel config to 5.4 for ramips Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
Diffstat (limited to 'target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch')
-rw-r--r--target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch21
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
new file mode 100644
index 0000000000..3310a6bdba
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
@@ -0,0 +1,21 @@
+--- a/arch/mips/pci/pci-mt7620.c
++++ b/arch/mips/pci/pci-mt7620.c
+@@ -35,6 +35,7 @@
+ #define PPLL_CFG1 0x9c
+
+ #define PPLL_DRV 0xa0
++#define PPLL_LD (1<<23)
+ #define PDRV_SW_SET (1<<31)
+ #define LC_CKDRVPD (1<<19)
+ #define LC_CKDRVOHZ (1<<18)
+@@ -242,8 +243,8 @@ static int mt7620_pci_hw_init(struct pla
+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
+ mdelay(100);
+
+- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
+- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
++ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
++ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
+ reset_control_assert(rstpcie0);
+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
+ return -1;