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authorDENG Qingfang <dengqf6@mail2.sysu.edu.cn>2020-03-01 17:06:45 +0800
committerChuanhong Guo <gch981213@gmail.com>2020-04-04 12:04:13 +0800
commit6be0da90a165912da7bd56e7bd4d7b2d978b4706 (patch)
tree00d4d9ccd7a62bfb84a0b27819c6c2145f759af1 /target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
parentd75c9b8f81b1a4f65132a5fed81f0a3fbbbd8fee (diff)
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ramips: refresh patches
Removed upstreamed/solved elsewhere upstream: - 0001-MIPS-ralink-Add-rt3352-SPI_CS1-pinmux.patch - 0002-MIPS-pci-rt2880-set-pci-controller-of_node.patch - 0004-MIPS-ralink-add-MT7621-pcie-driver.patch - 0009-PCI-MIPS-enable-PCIe-on-MT7688.patch - 0025-pinctrl-ralink-add-pinctrl-driver.patch - 0028-GPIO-ralink-add-mt7621-gpio-controller.patch - 0043-spi-add-mt7621-support.patch - 0045-i2c-add-mt7621-driver.patch - 0047-DMA-ralink-add-rt2880-dma-engine.patch - 0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch - 0054-mtd-spi-nor-w25q256-respect-default-mode.patch - 0099-pci-mt7620.patch - 304-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch Removed because of the new NAND driver: - 0038-Revert-mtd-nand-Remove-unused-chip-write_page-hook.patch - 0039-mtd-add-mt7621-nand-support.patch - 0040-nand-hack.patch Remove patch that no longer applies (needs rework): - 0034-NET-multi-phy-support.patch Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
Diffstat (limited to 'target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch')
-rw-r--r--target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch12
1 files changed, 6 insertions, 6 deletions
diff --git a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
index 3310a6bdba..7c00d4c9ae 100644
--- a/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
+++ b/target/linux/ramips/patches-5.4/999-fix-pci-init-mt7620.patch
@@ -1,14 +1,14 @@
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
-@@ -35,6 +35,7 @@
+@@ -32,6 +32,7 @@
#define PPLL_CFG1 0x9c
#define PPLL_DRV 0xa0
-+#define PPLL_LD (1<<23)
- #define PDRV_SW_SET (1<<31)
- #define LC_CKDRVPD (1<<19)
- #define LC_CKDRVOHZ (1<<18)
-@@ -242,8 +243,8 @@ static int mt7620_pci_hw_init(struct pla
++#define PPLL_LD BIT(23)
+ #define PDRV_SW_SET BIT(31)
+ #define LC_CKDRVPD BIT(19)
+ #define LC_CKDRVOHZ BIT(18)
+@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
mdelay(100);