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authorDENG Qingfang <dengqf6@mail2.sysu.edu.cn>2020-03-01 17:06:45 +0800
committerChuanhong Guo <gch981213@gmail.com>2020-04-04 12:04:13 +0800
commit6be0da90a165912da7bd56e7bd4d7b2d978b4706 (patch)
tree00d4d9ccd7a62bfb84a0b27819c6c2145f759af1 /target/linux/ramips/patches-5.4/0054-mtd-spi-nor-w25q256-respect-default-mode.patch
parentd75c9b8f81b1a4f65132a5fed81f0a3fbbbd8fee (diff)
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ramips: refresh patches
Removed upstreamed/solved elsewhere upstream: - 0001-MIPS-ralink-Add-rt3352-SPI_CS1-pinmux.patch - 0002-MIPS-pci-rt2880-set-pci-controller-of_node.patch - 0004-MIPS-ralink-add-MT7621-pcie-driver.patch - 0009-PCI-MIPS-enable-PCIe-on-MT7688.patch - 0025-pinctrl-ralink-add-pinctrl-driver.patch - 0028-GPIO-ralink-add-mt7621-gpio-controller.patch - 0043-spi-add-mt7621-support.patch - 0045-i2c-add-mt7621-driver.patch - 0047-DMA-ralink-add-rt2880-dma-engine.patch - 0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch - 0054-mtd-spi-nor-w25q256-respect-default-mode.patch - 0099-pci-mt7620.patch - 304-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch Removed because of the new NAND driver: - 0038-Revert-mtd-nand-Remove-unused-chip-write_page-hook.patch - 0039-mtd-add-mt7621-nand-support.patch - 0040-nand-hack.patch Remove patch that no longer applies (needs rework): - 0034-NET-multi-phy-support.patch Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
Diffstat (limited to 'target/linux/ramips/patches-5.4/0054-mtd-spi-nor-w25q256-respect-default-mode.patch')
-rw-r--r--target/linux/ramips/patches-5.4/0054-mtd-spi-nor-w25q256-respect-default-mode.patch73
1 files changed, 0 insertions, 73 deletions
diff --git a/target/linux/ramips/patches-5.4/0054-mtd-spi-nor-w25q256-respect-default-mode.patch b/target/linux/ramips/patches-5.4/0054-mtd-spi-nor-w25q256-respect-default-mode.patch
deleted file mode 100644
index a686937989..0000000000
--- a/target/linux/ramips/patches-5.4/0054-mtd-spi-nor-w25q256-respect-default-mode.patch
+++ /dev/null
@@ -1,73 +0,0 @@
---- a/drivers/mtd/spi-nor/spi-nor.c
-+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -142,20 +142,29 @@ static int read_fsr(struct spi_nor *nor)
- * location. Return the configuration register value.
- * Returns negative if error occurred.
- */
--static int read_cr(struct spi_nor *nor)
-+static int _read_cr(struct spi_nor *nor, u8 reg)
- {
- int ret;
- u8 val;
-
-- ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
-+ ret = nor->read_reg(nor, reg, &val, 1);
- if (ret < 0) {
-- dev_err(nor->dev, "error %d reading CR\n", ret);
-+ dev_err(nor->dev, "error %d reading %s\n", ret,
-+ (reg==SPINOR_OP_RDCR)?"CR":"XCR");
- return ret;
- }
-
- return val;
- }
-
-+static inline int read_cr(struct spi_nor *nor) {
-+ return _read_cr(nor, SPINOR_OP_RDCR);
-+}
-+
-+static inline int read_xcr(struct spi_nor *nor) {
-+ return _read_cr(nor, SPINOR_OP_RDXCR);
-+}
-+
- /*
- * Write status register 1 byte
- * Returns negative if error occurred.
-@@ -2898,9 +2907,16 @@ int spi_nor_scan(struct spi_nor *nor, co
- } else if (mtd->size > 0x1000000) {
- /* enable 4-byte addressing if the device exceeds 16MiB */
- nor->addr_width = 4;
-- if (info->flags & SPI_NOR_4B_READ_OP)
-- spi_nor_set_4byte_read(nor, info);
-- else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
-+ if (info->flags & SPI_NOR_4B_READ_OP) {
-+ if (JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
-+ ret = read_xcr(nor);
-+ if (!(ret > 0 && (ret & XCR_DEF_4B_ADDR_MODE)))
-+ spi_nor_set_4byte_read(nor, info);
-+ else
-+ set_4byte(nor, info, 1);
-+ } else
-+ spi_nor_set_4byte_read(nor, info);
-+ } else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
- info->flags & SPI_NOR_4B_OPCODES)
- spi_nor_set_4byte_opcodes(nor, info);
- else
---- a/include/linux/mtd/spi-nor.h
-+++ b/include/linux/mtd/spi-nor.h
-@@ -103,6 +103,7 @@
- #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
- #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
- #define SPINOR_OP_WREAR 0xc5 /* Write extended address register */
-+#define SPINOR_OP_RDXCR 0x15 /* Read extended configuration register */
-
- /* Used for Spansion flashes only. */
- #define SPINOR_OP_BRWR 0x17 /* Bank register write */
-@@ -135,6 +136,7 @@
-
- /* Configuration Register bits. */
- #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
-+#define XCR_DEF_4B_ADDR_MODE BIT(1) /* Winbond 4B mode default */
-
- /* Status Register 2 bits. */
- #define SR2_QUAD_EN_BIT7 BIT(7)