ramips: 5.10: port and refresh patches, ralink drv

Enable testing kernel.

Fix compile errors by using new kernel APIs.

Fix fuzz by manually editing patches to ensure the code goes in the
right place.

For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit
a307593a6 to keep the OpenWrt ralink driver operational.

Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693
and #3952.

Run automatic quilt refresh on the rest.

Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>

1 files changed, 19 insertions, 15 deletions

diff --git a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
index 08b4b0de29..07c7588661 100644
--- a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
+++ b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
@@ -44,7 +44,13 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  #define MT7621_CHIP_NAME1		0x20203132
 --- a/arch/mips/ralink/mt7621.c
 +++ b/arch/mips/ralink/mt7621.c
-@@ -13,6 +13,7 @@
+@@ -10,11 +10,13 @@
+ #include <linux/slab.h>
+ #include <linux/sys_soc.h>
+ #include <linux/jiffies.h>
++#include <linux/memblock.h>
+ #include <linux/clk.h>
+ #include <linux/clkdev.h>
  #include <linux/clk-provider.h>
  #include <dt-bindings/clock/mt7621-clk.h>
  
@@ -52,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  #include <asm/mipsregs.h>
  #include <asm/smp-ops.h>
  #include <asm/mips-cps.h>
-@@ -55,6 +56,8 @@
+@@ -57,6 +59,8 @@
  #define MT7621_GPIO_MODE_SDHCI_SHIFT	18
  #define MT7621_GPIO_MODE_SDHCI_GPIO	1
  
@@ -61,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
  static struct rt2880_pmx_func uart3_grp[] = {
-@@ -139,6 +142,28 @@ static struct clk *__init mt7621_add_sys
+@@ -141,6 +145,26 @@ static struct clk *__init mt7621_add_sys
  	return clk;
  }
  
@@ -71,26 +77,24 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
 +	phys_addr_t size;
 +
 +	for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
-+		if (!memcmp(dm, dm + size, sizeof(detect_magic)))
++		if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
 +			break;
 +	}
 +
 +	if ((size == 256 * SZ_1M) &&
 +	    (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
-+	    memcmp(dm, dm + size, sizeof(detect_magic))) {
-+		add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE,
-+				  BOOT_MEM_RAM);
-+		add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE,
-+				  BOOT_MEM_RAM);
++	    __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
++		memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
++		memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
 +	} else {
-+		add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM);
++		memblock_add(MT7621_LOWMEM_BASE, size);
 +	}
 +}
 +
  void __init ralink_clk_init(void)
  {
  	u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
-@@ -317,10 +342,7 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -346,10 +370,7 @@ void prom_soc_init(struct ralink_soc_inf
  		(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
  		(rev & CHIP_REV_ECO_MASK));
  
@@ -101,7 +105,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
 +	soc_info->mem_detect = mt7621_memory_detect;
  	rt2880_pinmux_data = mt7621_pinmux_data;
  
- 
+ 	soc_dev_init(soc_info, rev);
 --- a/arch/mips/ralink/common.h
 +++ b/arch/mips/ralink/common.h
 @@ -17,6 +17,7 @@ struct ralink_soc_info {
@@ -114,12 +118,12 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  
 --- a/arch/mips/ralink/of.c
 +++ b/arch/mips/ralink/of.c
-@@ -87,6 +87,8 @@ void __init plat_mem_setup(void)
+@@ -85,6 +85,8 @@ void __init plat_mem_setup(void)
  	of_scan_flat_dt(early_init_dt_find_memory, NULL);
  	if (memory_dtb)
  		of_scan_flat_dt(early_init_dt_scan_memory, NULL);
 +	else if (soc_info.mem_detect)
 +		soc_info.mem_detect();
  	else if (soc_info.mem_size)
- 		add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
- 				  BOOT_MEM_RAM);
+ 		memblock_add(soc_info.mem_base, soc_info.mem_size * SZ_1M);
+ 	else