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authorJohn Crispin <john@phrozen.org>2017-02-13 12:38:27 +0100
committerJohn Crispin <john@phrozen.org>2017-02-14 12:17:52 +0100
commit9c2422709075196022fcbc2d0f5f83e01d02b951 (patch)
tree4f18a4dd9d22fcbe10c0365596dd133cf28383be /target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch
parentd5221d5a419c14456bccba9f6825567839082fb0 (diff)
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ramips: add v4.9 support
NAND support is missing Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch')
-rw-r--r--target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch42
1 files changed, 42 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch b/target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch
new file mode 100644
index 0000000000..e87e979a85
--- /dev/null
+++ b/target/linux/ramips/patches-4.9/0700-pinctrl-mt7620-mdio-as-refclk.patch
@@ -0,0 +1,42 @@
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -115,9 +115,14 @@
+ #define MT7620_GPIO_MODE_WDT_MASK 0x3
+ #define MT7620_GPIO_MODE_WDT_SHIFT 21
+
++#define MT7620_GPIO_MODE_MDIO 0
++#define MT7620_GPIO_MODE_MDIO_REFCLK 1
++#define MT7620_GPIO_MODE_MDIO_GPIO 2
++#define MT7620_GPIO_MODE_MDIO_MASK 0x3
++#define MT7620_GPIO_MODE_MDIO_SHIFT 7
++
+ #define MT7620_GPIO_MODE_I2C 0
+ #define MT7620_GPIO_MODE_UART1 5
+-#define MT7620_GPIO_MODE_MDIO 8
+ #define MT7620_GPIO_MODE_RGMII1 9
+ #define MT7620_GPIO_MODE_RGMII2 10
+ #define MT7620_GPIO_MODE_SPI 11
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -55,7 +55,10 @@ static int dram_type;
+ static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
+ static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
+ static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+-static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func mdio_grp[] = {
++ FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
++ FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
++};
+ static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
+ static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
+ static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
+@@ -92,7 +95,8 @@ static struct rt2880_pmx_group mt7620a_p
+ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
+ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
+- GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
++ GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
++ MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
+ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
+ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
+ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,