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| author | Felix Fietkau <nbd@nbd.name> | 2017-07-20 12:57:44 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2017-11-02 15:58:45 +0100 |
| commit | 22d982ea003360d86ff1fef5114fb41dfa09ce9b (patch) | |
| tree | 75ff15cf3401bca8d36f5afe9c1f5927dde805e4 /target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch | |
| parent | f90f94d2c183dde6c214bc5068c33085d5f53290 (diff) | |
| download | upstream-22d982ea003360d86ff1fef5114fb41dfa09ce9b.tar.gz upstream-22d982ea003360d86ff1fef5114fb41dfa09ce9b.tar.bz2 upstream-22d982ea003360d86ff1fef5114fb41dfa09ce9b.zip | |
ramips: add support for switching between 3-byte and 4-byte addressing on w25q256 flash
On some devices the flash chip needs to be in 3-byte addressing mode during
reboot, otherwise the boot loader will fail to start.
This mode however does not allow regular reads/writes onto the upper 16M
half. W25Q256 has separate read commands for reading from >16M, however
it does not have any separate write commands.
This patch changes the code to leave the chip in 3-byte mode most of the
time and only switch during erase/write cycles that go to >16M
addresses.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch')
| -rw-r--r-- | target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch index 40994fb8d3..7f88ec52a7 100644 --- a/target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch +++ b/target/linux/ramips/patches-4.9/0054-mtd-add-chunked-read-io-to-m25p80.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -1381,6 +1381,66 @@ write_err: +@@ -1453,6 +1453,67 @@ write_err: return ret; } @@ -8,6 +8,7 @@ + size_t *_retlen, const u_char *_buf) +{ + struct spi_nor *nor = mtd_to_spi_nor(mtd); ++ u32 addr_width = nor->addr_width + !!(nor->flags & SNOR_F_4B_EXT_ADDR); + int chunk_size; + int retlen = 0; + int ret; @@ -16,8 +17,8 @@ + if (!chunk_size) + chunk_size = _len; + -+ if (nor->addr_width > 3) -+ chunk_size -= nor->addr_width - 3; ++ if (addr_width > 3) ++ chunk_size -= addr_width - 3; + + while (retlen < _len) { + size_t len = min_t(int, chunk_size, _len - retlen); @@ -67,7 +68,7 @@ static int macronix_quad_enable(struct spi_nor *nor) { int ret, val; -@@ -1630,10 +1690,12 @@ int spi_nor_scan(struct spi_nor *nor, co +@@ -1702,10 +1763,12 @@ int spi_nor_scan(struct spi_nor *nor, co } /* sst nor chips use AAI word program */ @@ -82,7 +83,7 @@ if (info->flags & USE_FSR) nor->flags |= SNOR_F_USE_FSR; -@@ -1663,11 +1725,20 @@ int spi_nor_scan(struct spi_nor *nor, co +@@ -1735,11 +1798,20 @@ int spi_nor_scan(struct spi_nor *nor, co mtd->writebufsize = nor->page_size; if (np) { @@ -105,15 +106,15 @@ nor->flash_read = SPI_NOR_FAST; --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h -@@ -141,6 +141,7 @@ enum spi_nor_option_flags { - SNOR_F_NO_OP_CHIP_ERASE = BIT(2), +@@ -143,6 +143,7 @@ enum spi_nor_option_flags { SNOR_F_S3AN_ADDR_DEFAULT = BIT(3), SNOR_F_READY_XSR_RDY = BIT(4), -+ SNOR_F_SST = BIT(5), + SNOR_F_4B_EXT_ADDR = BIT(5), ++ SNOR_F_SST = BIT(6), }; /** -@@ -180,6 +181,7 @@ struct spi_nor { +@@ -182,6 +183,7 @@ struct spi_nor { struct mutex lock; struct device *dev; u32 page_size; |