diff options
| author | Etienne Haarsma <bladeoner112@gmail.com> | 2017-11-26 12:34:38 +0100 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-11-26 15:10:36 +0100 |
| commit | 7f3dab2fc34e9b6c15d74ebf8e1d74ef601677e3 (patch) | |
| tree | 8cbc6fae4a42b846360e5c6467f0ddb8896f5c8f /target/linux/ramips/patches-4.4/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch | |
| parent | d3f40aabba83818106ce840dba9f7e76a06e721d (diff) | |
| download | upstream-7f3dab2fc34e9b6c15d74ebf8e1d74ef601677e3.tar.gz upstream-7f3dab2fc34e9b6c15d74ebf8e1d74ef601677e3.tar.bz2 upstream-7f3dab2fc34e9b6c15d74ebf8e1d74ef601677e3.zip | |
kernel: bump 4.4 to 4.4.102
Refreshed all patches.
Removed upstream ramips patch: 0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch
Compile-tested: ar71xx
Run-tested: ar71xx
Signed-off-by: Etienne Haarsma <bladeoner112@gmail.com>
Tested-by: Stijn Segers <francesco.borromini@inventati.org>
Diffstat (limited to 'target/linux/ramips/patches-4.4/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch')
| -rw-r--r-- | target/linux/ramips/patches-4.4/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/target/linux/ramips/patches-4.4/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch b/target/linux/ramips/patches-4.4/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch deleted file mode 100644 index 55fd70131d..0000000000 --- a/target/linux/ramips/patches-4.4/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- a/arch/mips/include/asm/mips-cm.h -+++ b/arch/mips/include/asm/mips-cm.h -@@ -238,8 +238,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) - #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) - #define CM_GCR_BASE_CMDEFTGT_SHF 0 - #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) --#define CM_GCR_BASE_CMDEFTGT_DISABLED 0 --#define CM_GCR_BASE_CMDEFTGT_MEM 1 -+#define CM_GCR_BASE_CMDEFTGT_MEM 0 - #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 - #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 - |