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authorRoman Yeryomin <roman@advem.lv>2018-01-17 00:07:58 +0200
committerJohn Crispin <john@phrozen.org>2018-02-15 10:46:39 +0100
commitf4e5880d0f3496a3151fe24d87ca2d08d3403a83 (patch)
treeb2a3f276e4786d7eed8d928cd8984975334556cf /target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch
parenta3b9cbafc33a94606368226020e7b69ff85f1115 (diff)
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ramips: preliminary support for 4.14
- removed upstreamed patches - 0901-spansion_nand_id_fix.patch is disabled, not clear if it's needed Signed-off-by: Roman Yeryomin <roman@advem.lv> Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch')
-rw-r--r--target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch21
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch b/target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch
new file mode 100644
index 0000000000..3310a6bdba
--- /dev/null
+++ b/target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch
@@ -0,0 +1,21 @@
+--- a/arch/mips/pci/pci-mt7620.c
++++ b/arch/mips/pci/pci-mt7620.c
+@@ -35,6 +35,7 @@
+ #define PPLL_CFG1 0x9c
+
+ #define PPLL_DRV 0xa0
++#define PPLL_LD (1<<23)
+ #define PDRV_SW_SET (1<<31)
+ #define LC_CKDRVPD (1<<19)
+ #define LC_CKDRVOHZ (1<<18)
+@@ -242,8 +243,8 @@ static int mt7620_pci_hw_init(struct pla
+ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
+ mdelay(100);
+
+- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
+- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
++ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
++ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
+ reset_control_assert(rstpcie0);
+ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
+ return -1;