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authorJohn Crispin <john@openwrt.org>2013-07-22 13:52:32 +0000
committerJohn Crispin <john@openwrt.org>2013-07-22 13:52:32 +0000
commit5525b2136e90fcfc8823b519fa4aa2499f0120ba (patch)
treee614278bc48faf84a9ff7de35d9de77b7e630fb6 /target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch
parentec6954e64e7cd7e503b62ab73381cfa0adce24fc (diff)
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ralink: set v3.10 as default
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37497
Diffstat (limited to 'target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch')
-rw-r--r--target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch59
1 files changed, 0 insertions, 59 deletions
diff --git a/target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch
deleted file mode 100644
index b56a734d01..0000000000
--- a/target/linux/ramips/patches-3.9/0133-MIPS-ralink-add-verbose-pmu-info.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From c7150f86dfb0fe2613af3c5bd1c0c587130b9460 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 20 May 2013 20:57:09 +0200
-Subject: [PATCH 133/164] MIPS: ralink: add verbose pmu info
-
-Print the PMU and LDO settings on boot.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -20,6 +20,22 @@
-
- #include "common.h"
-
-+/* analog */
-+#define PMU0_CFG 0x88
-+#define PMU_SW_SET BIT(28)
-+#define A_DCDC_EN BIT(24)
-+#define A_SSC_PERI BIT(19)
-+#define A_SSC_GEN BIT(18)
-+#define A_SSC_M 0x3
-+#define A_SSC_S 16
-+#define A_DLY_M 0x7
-+#define A_DLY_S 8
-+#define A_VTUNE_M 0xff
-+
-+/* digital */
-+#define PMU1_CFG 0x8C
-+#define DIG_SW_SEL BIT(25)
-+
- /* does the board have sdram or ddram */
- static int dram_type;
-
-@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_inf
- u32 n1;
- u32 rev;
- u32 cfg0;
-+ u32 pmu0;
-+ u32 pmu1;
-
- n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_inf
- BUG();
- }
- soc_info->mem_base = MT7620_DRAM_BASE;
-+
-+ pmu0 = __raw_readl(sysc + PMU0_CFG);
-+ pmu1 = __raw_readl(sysc + PMU1_CFG);
-+
-+ pr_info("Analog PMU set to %s control\n",
-+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
-+ pr_info("Digital PMU set to %s control\n",
-+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
- }