ramips: sync kernel patches with the mips-next tree

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 36431

1 files changed, 47 insertions, 0 deletions

diff --git a/target/linux/ramips/patches-3.8/0103-MIPS-ralink-fix-RT305x-clock-setup.patch b/target/linux/ramips/patches-3.8/0103-MIPS-ralink-fix-RT305x-clock-setup.patch
new file mode 100644
index 0000000000..7d682e75bd
--- /dev/null
+++ b/target/linux/ramips/patches-3.8/0103-MIPS-ralink-fix-RT305x-clock-setup.patch
@@ -0,0 +1,47 @@
+From 845f786c561c0991d9b4088a2d77b8fd4831d487 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 22 Mar 2013 19:25:59 +0100
+Subject: [PATCH 103/137] MIPS: ralink: fix RT305x clock setup
+
+Add a few missing clocks.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5167/
+---
+ arch/mips/ralink/rt305x.c |   12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -124,6 +124,8 @@ struct ralink_pinmux gpio_pinmux = {
+ void __init ralink_clk_init(void)
+ {
+ 	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
++	unsigned long wmac_rate = 40000000;
++
+ 	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+ 
+ 	if (soc_is_rt305x() || soc_is_rt3350()) {
+@@ -176,11 +178,21 @@ void __init ralink_clk_init(void)
+ 		BUG();
+ 	}
+ 
++	if (soc_is_rt3352() || soc_is_rt5350()) {
++		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
++
++		if (!(val & RT3352_CLKCFG0_XTAL_SEL))
++			wmac_rate = 20000000;
++	}
++
+ 	ralink_clk_add("cpu", cpu_rate);
+ 	ralink_clk_add("10000b00.spi", sys_rate);
+ 	ralink_clk_add("10000100.timer", wdt_rate);
++	ralink_clk_add("10000120.watchdog", wdt_rate);
+ 	ralink_clk_add("10000500.uart", uart_rate);
+ 	ralink_clk_add("10000c00.uartlite", uart_rate);
++	ralink_clk_add("10100000.ethernet", sys_rate);
++	ralink_clk_add("10180000.wmac", wmac_rate);
+ }
+ 
+ void __init ralink_of_remap(void)