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authorJohn Crispin <john@openwrt.org>2013-06-23 15:50:49 +0000
committerJohn Crispin <john@openwrt.org>2013-06-23 15:50:49 +0000
commit55fb6f3a05deb4a8b5e600cc10bae9555a9f90be (patch)
treea2ef24cfc434f5eb47364d944947588c5d51fc69 /target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch
parent43a3d87b8370872c5720b4bb6616b797486d38d8 (diff)
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ralink: update patches
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37016
Diffstat (limited to 'target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch')
-rw-r--r--target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch37
1 files changed, 37 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch b/target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch
new file mode 100644
index 0000000000..8ecaea20ab
--- /dev/null
+++ b/target/linux/ramips/patches-3.8/0021-MIPS-ralink-add-RT5350-sdram-register-defines.patch
@@ -0,0 +1,37 @@
+From 0df8c2fdd0fe1095b834fbf2b098d6f1b3e56608 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 25 Mar 2013 11:19:58 +0100
+Subject: [PATCH 21/79] MIPS: ralink: add RT5350 sdram register defines
+
+Add a few missing defines that are needed to make memory detection work on the
+RT5350.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5169/
+---
+ arch/mips/include/asm/mach-ralink/rt305x.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
+index e36c3c5..80cda8a 100644
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -97,6 +97,14 @@ static inline int soc_is_rt5350(void)
+ #define RT5350_SYSCFG0_CPUCLK_320 0x2
+ #define RT5350_SYSCFG0_CPUCLK_300 0x3
+
++#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
++#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
++#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
++#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
++#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
++#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
++#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
++
+ /* multi function gpio pins */
+ #define RT305X_GPIO_I2C_SD 1
+ #define RT305X_GPIO_I2C_SCLK 2
+--
+1.7.10.4
+