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authorJohn Crispin <john@openwrt.org>2015-08-17 06:18:30 +0000
committerJohn Crispin <john@openwrt.org>2015-08-17 06:18:30 +0000
commitaa4c6e27b42b4c4be07462c7e951a694fe38f500 (patch)
treeb463a0a8cb4d81b35986046050a3b068d2f31054 /target/linux/ramips/patches-3.18/0070-pci-reset.patch
parentb0b59a8e75242f1b9715dabf834df97d48d42cbc (diff)
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ramips: reorder patches
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 46659
Diffstat (limited to 'target/linux/ramips/patches-3.18/0070-pci-reset.patch')
-rw-r--r--target/linux/ramips/patches-3.18/0070-pci-reset.patch35
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.18/0070-pci-reset.patch b/target/linux/ramips/patches-3.18/0070-pci-reset.patch
new file mode 100644
index 0000000000..6055731822
--- /dev/null
+++ b/target/linux/ramips/patches-3.18/0070-pci-reset.patch
@@ -0,0 +1,35 @@
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -11,6 +11,7 @@
+ #include <linux/pm.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
++#include <linux/delay.h>
+ #include <linux/reset-controller.h>
+
+ #include <asm/reboot.h>
+@@ -18,8 +19,10 @@
+ #include <asm/mach-ralink/ralink_regs.h>
+
+ /* Reset Control */
+-#define SYSC_REG_RESET_CTRL 0x034
+-#define RSTCTL_RESET_SYSTEM BIT(0)
++#define SYSC_REG_RESET_CTRL 0x034
++
++#define RSTCTL_RESET_PCI BIT(26)
++#define RSTCTL_RESET_SYSTEM BIT(0)
+
+ static int ralink_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+@@ -83,6 +86,11 @@ void ralink_rst_init(void)
+
+ static void ralink_restart(char *command)
+ {
++ if (IS_ENABLED(CONFIG_PCI)) {
++ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
++ mdelay(50);
++ }
++
+ local_irq_disable();
+ rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
+ unreachable();