ralink: update pcie driver to load ranges from dts

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 43249

1 files changed, 17 insertions, 27 deletions

diff --git a/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
index 3b6b56dc46..91f5feac89 100644
--- a/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
+++ b/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
@@ -6,28 +6,28 @@ Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  arch/mips/pci/Makefile      |    1 +
- arch/mips/pci/pci-mt7620a.c |  363 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/pci/pci-mt7620.c  |  363 +++++++++++++++++++++++++++++++++++++++++++
  arch/mips/ralink/Kconfig    |    1 +
  3 files changed, 365 insertions(+)
- create mode 100644 arch/mips/pci/pci-mt7620a.c
+ create mode 100644 arch/mips/pci/pci-mt7620.c
 
 Index: linux-3.14.18/arch/mips/pci/Makefile
 ===================================================================
---- linux-3.14.18.orig/arch/mips/pci/Makefile	2014-11-12 15:57:29.098559332 +0100
-+++ linux-3.14.18/arch/mips/pci/Makefile	2014-11-12 15:57:29.118560067 +0100
+--- linux-3.14.18.orig/arch/mips/pci/Makefile	2014-11-13 15:45:37.323344081 +0100
++++ linux-3.14.18/arch/mips/pci/Makefile	2014-11-13 15:45:37.331344390 +0100
 @@ -42,6 +42,7 @@
  obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
  obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
  obj-$(CONFIG_SOC_MT7621)	+= pci-mt7621.o
-+obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620a.o
++obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
  obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
  obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
  obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
-Index: linux-3.14.18/arch/mips/pci/pci-mt7620a.c
+Index: linux-3.14.18/arch/mips/pci/pci-mt7620.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-3.14.18/arch/mips/pci/pci-mt7620a.c	2014-11-12 17:24:58.339670670 +0100
-@@ -0,0 +1,405 @@
++++ linux-3.14.18/arch/mips/pci/pci-mt7620.c	2014-11-13 18:20:27.961225097 +0100
+@@ -0,0 +1,395 @@
 +/*
 + *  Ralink MT7620A SoC PCI support
 + *
@@ -228,19 +228,8 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620a.c
 +	.write	= pci_config_write,
 +};
 +
-+static struct resource mt7620_res_pci_mem1 = {
-+	.name	= "pci memory",
-+	.start	= RALINK_PCI_MM_MAP_BASE,
-+	.end	= (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
-+	.flags	= IORESOURCE_MEM,
-+};
-+static struct resource mt7620_res_pci_io1 = {
-+	.name	= "pci io",
-+	.start	= RALINK_PCI_IO_MAP_BASE,
-+	.end	= (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
-+	.flags	= IORESOURCE_IO,
-+};
-+
++static struct resource mt7620_res_pci_mem1;
++static struct resource mt7620_res_pci_io1;
 +struct pci_controller mt7620_controller = {
 +	.pci_ops	= &mt7620_pci_ops,
 +	.mem_resource	= &mt7620_res_pci_mem1,
@@ -325,7 +314,7 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620a.c
 +	ioport_resource.end = ~0;
 +
 +	/* bring up the pci core */
-+	switch (mt762x_soc) {
++	switch (ralink_soc) {
 +	case MT762X_SOC_MT7620A:
 +		if (mt7620_pci_hw_init(pdev))
 +			return -1;
@@ -350,7 +339,7 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620a.c
 +	if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 +		reset_control_assert(rstpcie0);
 +		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+		if (mt762x_soc == MT762X_SOC_MT7620A)
++		if (ralink_soc == MT762X_SOC_MT7620A)
 +			rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
 +		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
 +		return -1;
@@ -393,6 +382,7 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620a.c
 +		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 +		return 0;
 +	}
++	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
 +
 +	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 +	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
@@ -435,8 +425,8 @@ Index: linux-3.14.18/arch/mips/pci/pci-mt7620a.c
 +arch_initcall(mt7620_pci_init);
 Index: linux-3.14.18/arch/mips/ralink/Kconfig
 ===================================================================
---- linux-3.14.18.orig/arch/mips/ralink/Kconfig	2014-11-12 15:57:29.098559332 +0100
-+++ linux-3.14.18/arch/mips/ralink/Kconfig	2014-11-12 15:57:29.118560067 +0100
+--- linux-3.14.18.orig/arch/mips/ralink/Kconfig	2014-11-13 15:45:37.323344081 +0100
++++ linux-3.14.18/arch/mips/ralink/Kconfig	2014-11-13 15:45:37.331344390 +0100
 @@ -39,6 +39,7 @@
  		bool "MT7620/8"
  		select USB_ARCH_HAS_OHCI
@@ -447,8 +437,8 @@ Index: linux-3.14.18/arch/mips/ralink/Kconfig
  		bool "MT7621"
 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h
 ===================================================================
---- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/mt7620.h	2014-11-12 15:57:29.082558746 +0100
-+++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h	2014-11-12 15:57:29.118560067 +0100
+--- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/mt7620.h	2014-11-13 15:45:37.311343619 +0100
++++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h	2014-11-13 18:20:31.721370073 +0100
 @@ -19,6 +19,7 @@
  	MT762X_SOC_MT7620N,
  	MT762X_SOC_MT7628AN,