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authorJohn Crispin <john@openwrt.org>2014-08-07 14:41:19 +0000
committerJohn Crispin <john@openwrt.org>2014-08-07 14:41:19 +0000
commitbc67bd229555f708717cd7647429f64b4c563a52 (patch)
tree09c23e958577e32fef82db5d7c1821e3049cea17 /target/linux/ramips/patches-3.14/0001-MIPS-ralink-add-verbose-pmu-info.patch
parente41a0cafff16f2443e587884782172c6d8478771 (diff)
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ralink: add 3.14 support
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 42040
Diffstat (limited to 'target/linux/ramips/patches-3.14/0001-MIPS-ralink-add-verbose-pmu-info.patch')
-rw-r--r--target/linux/ramips/patches-3.14/0001-MIPS-ralink-add-verbose-pmu-info.patch64
1 files changed, 64 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.14/0001-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.14/0001-MIPS-ralink-add-verbose-pmu-info.patch
new file mode 100644
index 0000000000..51094d59b2
--- /dev/null
+++ b/target/linux/ramips/patches-3.14/0001-MIPS-ralink-add-verbose-pmu-info.patch
@@ -0,0 +1,64 @@
+From 453850d315070678245f61202ae343153589e5a6 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:16:50 +0100
+Subject: [PATCH 01/57] MIPS: ralink: add verbose pmu info
+
+Print the PMU and LDO settings on boot.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index a3ad56c..5846817 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -20,6 +20,22 @@
+
+ #include "common.h"
+
++/* analog */
++#define PMU0_CFG 0x88
++#define PMU_SW_SET BIT(28)
++#define A_DCDC_EN BIT(24)
++#define A_SSC_PERI BIT(19)
++#define A_SSC_GEN BIT(18)
++#define A_SSC_M 0x3
++#define A_SSC_S 16
++#define A_DLY_M 0x7
++#define A_DLY_S 8
++#define A_VTUNE_M 0xff
++
++/* digital */
++#define PMU1_CFG 0x8C
++#define DIG_SW_SEL BIT(25)
++
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+@@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+ u32 n1;
+ u32 rev;
+ u32 cfg0;
++ u32 pmu0;
++ u32 pmu1;
+
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+@@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+ BUG();
+ }
+ soc_info->mem_base = MT7620_DRAM_BASE;
++
++ pmu0 = __raw_readl(sysc + PMU0_CFG);
++ pmu1 = __raw_readl(sysc + PMU1_CFG);
++
++ pr_info("Analog PMU set to %s control\n",
++ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
++ pr_info("Digital PMU set to %s control\n",
++ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+ }
+--
+1.7.10.4
+