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authorJohn Crispin <john@openwrt.org>2013-08-14 18:15:15 +0000
committerJohn Crispin <john@openwrt.org>2013-08-14 18:15:15 +0000
commit9e5b0cc19cebf6ed876c7eace13b887b46e518c0 (patch)
treef246f12adca3e91f5e3708e97c7a4add05cc0ce3 /target/linux/ramips/patches-3.10/0013-MIPS-ralink-mt7620-add-verbose-ram-info.patch
parent2864fb107f00531df0b114d52334d3e00fa5d6c2 (diff)
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ramips: update v3.10 patches
Sync the patches with those sent upstream for v3.12. Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 37778
Diffstat (limited to 'target/linux/ramips/patches-3.10/0013-MIPS-ralink-mt7620-add-verbose-ram-info.patch')
-rw-r--r--target/linux/ramips/patches-3.10/0013-MIPS-ralink-mt7620-add-verbose-ram-info.patch34
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.10/0013-MIPS-ralink-mt7620-add-verbose-ram-info.patch b/target/linux/ramips/patches-3.10/0013-MIPS-ralink-mt7620-add-verbose-ram-info.patch
new file mode 100644
index 0000000000..f82446a28b
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0013-MIPS-ralink-mt7620-add-verbose-ram-info.patch
@@ -0,0 +1,34 @@
+From 2d17c793a9cd3f67351d1a15c099ef2464e81f47 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 20 May 2013 20:30:11 +0200
+Subject: [PATCH 13/25] MIPS: ralink: mt7620: add verbose ram info
+
+Make the code print which of SDRAM, DDR1 or DDR2 was detected.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_inf
+
+ switch (dram_type) {
+ case SYSCFG0_DRAM_TYPE_SDRAM:
++ pr_info("Board has SDRAM\n");
+ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+ break;
+
+ case SYSCFG0_DRAM_TYPE_DDR1:
++ pr_info("Board has DDR1\n");
+ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+ break;
+
+ case SYSCFG0_DRAM_TYPE_DDR2:
++ pr_info("Board has DDR2\n");
+ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+ break;