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| author | John Crispin <blogic@openwrt.org> | 2013-07-15 10:06:55 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2013-07-15 10:06:55 +0000 |
| commit | 0b4bd54afbc7e56194c7974e3cc282dbd0862953 (patch) | |
| tree | faa96127d83945d5237ce1c294b2316754727325 /target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | |
| parent | dfe23e06f6f54927522d5b4bac6d2ac647bf0c23 (diff) | |
| download | upstream-0b4bd54afbc7e56194c7974e3cc282dbd0862953.tar.gz upstream-0b4bd54afbc7e56194c7974e3cc282dbd0862953.tar.bz2 upstream-0b4bd54afbc7e56194c7974e3cc282dbd0862953.zip | |
ramips: add ralink v3.10 support
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37331 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch new file mode 100644 index 0000000000..ebb58980f7 --- /dev/null +++ b/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch @@ -0,0 +1,25 @@ +From 5340673ba16e3c8c9c1406d5ab84aca82e83e2ce Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 23 May 2013 18:46:25 +0200 +Subject: [PATCH 10/33] MIPS: ralink: add spi clock definition to mt7620a + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 62356a0..96422e5 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -183,6 +183,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("10000100.timer", 40000000); + ralink_clk_add("10000500.uart", 40000000); ++ ralink_clk_add("10000b00.spi", 40000000); + ralink_clk_add("10000c00.uartlite", 40000000); + } + +-- +1.7.10.4 + |