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authorGabor Juhos <juhosg@openwrt.org>2010-01-26 09:57:38 +0000
committerGabor Juhos <juhosg@openwrt.org>2010-01-26 09:57:38 +0000
commitb34feab713e53f9c6d852c2c256438e936744ab4 (patch)
treef21d954cef6d0d5ceff33b04bb4c5a07946c4a32 /target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch
parentc5ac3f64aba4ee79db164618f00727dfca0d9ade (diff)
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ramips: add preliminary support for 2.6.32
SVN-Revision: 19343
Diffstat (limited to 'target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch')
-rw-r--r--target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch56
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch b/target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch
new file mode 100644
index 0000000000..894eed1e5b
--- /dev/null
+++ b/target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch
@@ -0,0 +1,56 @@
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -16,6 +16,22 @@
+ #include <asm/cevt-r4k.h>
+
+ /*
++ * Compare interrupt can be routed and latched outside the core,
++ * so a single execution hazard barrier may not be enough to give
++ * it time to clear as seen in the Cause register. 4 time the
++ * pipeline depth seems reasonably conservative, and empirically
++ * works better in configurations with high CPU/bus clock ratios.
++ */
++
++#define compare_change_hazard() \
++ do { \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ irq_disable_hazard(); \
++ } while (0)
++
++/*
+ * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
+ * of these routines with SMTC-specific variants.
+ */
+@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
+ cnt = read_c0_count();
+ cnt += delta;
+ write_c0_compare(cnt);
++ compare_change_hazard();
+ res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
+ return res;
+ }
+@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
+ return (read_c0_cause() >> cp0_compare_irq) & 0x100;
+ }
+
+-/*
+- * Compare interrupt can be routed and latched outside the core,
+- * so a single execution hazard barrier may not be enough to give
+- * it time to clear as seen in the Cause register. 4 time the
+- * pipeline depth seems reasonably conservative, and empirically
+- * works better in configurations with high CPU/bus clock ratios.
+- */
+-
+-#define compare_change_hazard() \
+- do { \
+- irq_disable_hazard(); \
+- irq_disable_hazard(); \
+- irq_disable_hazard(); \
+- irq_disable_hazard(); \
+- } while (0)
+-
+ int c0_compare_int_usable(void)
+ {
+ unsigned int delta;