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| author | John Crispin <blogic@openwrt.org> | 2015-02-09 19:34:49 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2015-02-09 19:34:49 +0000 |
| commit | d8e190575f99359deb58db67addf225904d32147 (patch) | |
| tree | e1edaf23d87d3efed3307a026740682fa8c602a9 /target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c | |
| parent | 52a82a73ae6d700f03cd8435f9070f154de30918 (diff) | |
| download | upstream-d8e190575f99359deb58db67addf225904d32147.tar.gz upstream-d8e190575f99359deb58db67addf225904d32147.tar.bz2 upstream-d8e190575f99359deb58db67addf225904d32147.zip | |
ralink: fix hw status almost full not work on mt7620 and mt7621
the old FE_INT_STATUS register becomes two registers.
FE_INT_STATUS and INT_STATUS. so the hw status almost full
must change to read from FE_INT_STATUS register.
tx/rx done read from INT_STATUS register.
mt7620 datasheet define CNT_GDM1_AF at BIT(29).
but after test it should be BIT(13). why?
Signed-off-by: michael lee <igvtee@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44371 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c index ebe85b9a6a..715221b100 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c @@ -65,6 +65,7 @@ struct fe_soc_data rt2880_data = { .checksum_bit = RX_DMA_L4VALID, .rx_int = FE_RX_DONE_INT, .tx_int = FE_TX_DONE_INT, + .status_int = FE_CNT_GDM_AF, .mdio_read = rt2880_mdio_read, .mdio_write = rt2880_mdio_write, .mdio_adjust_link = rt2880_mdio_link_adjust, |