diff options
| author | Michael Pratt <mcpratt@pm.me> | 2021-05-31 03:56:20 -0400 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2022-04-19 14:48:21 +0200 |
| commit | 6685eb29e507ee3e6f913290c54767ba63e2ce80 (patch) | |
| tree | 19347ed1b7d2430623bf680cce55e7389bc3df67 /target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c | |
| parent | 47db830b827c55c7d301f4244d2270e6bd45153d (diff) | |
| download | upstream-6685eb29e507ee3e6f913290c54767ba63e2ce80.tar.gz upstream-6685eb29e507ee3e6f913290c54767ba63e2ce80.tar.bz2 upstream-6685eb29e507ee3e6f913290c54767ba63e2ce80.zip | |
ramips: mt7620: add ephy-disable option to switch driver
Add back the register write to disable internal PHYs
as a separate option in the code that can be set using a DTS property.
Set the option to true by default
when an external mt7530 switch is identified.
This makes the driver more in sync with original SDK code
while keeping the lines separated into different options
to accommodate any board with any PHY layout.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit cc6fd6fbb505071e08011f7998afaffefcf08fd3)
Diffstat (limited to 'target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c index 67f70f286d..ae90f0484d 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c @@ -73,7 +73,13 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw) /* Enable MIB stats */ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN); - if (gsw->ephy_base) { + if (gsw->ephy_disable) { + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) | + (gsw->ephy_base << 16) | (0x1f << 24), + GSW_REG_GPC1); + + pr_info("gsw: internal ephy disabled\n"); + } else if (gsw->ephy_base) { mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) | (gsw->ephy_base << 16), GSW_REG_GPC1); @@ -194,13 +200,17 @@ int mtk_gsw_init(struct fe_priv *priv) gsw = platform_get_drvdata(pdev); priv->soc->swpriv = gsw; + gsw->ephy_disable = of_property_read_bool(np, "mediatek,ephy-disable"); + mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus"); if (mdiobus_node) { for_each_child_of_node(mdiobus_node, phy_node) { id = of_get_property(phy_node, "reg", NULL); if (id && (be32_to_cpu(*id) == 0x1f)) - of_node_put(mdiobus_node); + gsw->ephy_disable = true; } + + of_node_put(mdiobus_node); } gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac"); |