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| author | Michael Pratt <mcpratt@pm.me> | 2021-05-01 14:47:01 -0400 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2022-04-19 14:48:21 +0200 |
| commit | 30e47fb1e4f128e76b10fa3e0ff55c0497a9096a (patch) | |
| tree | 4be79c719a65399f11267a45964fc3682f22d542 /target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c | |
| parent | 3f976d0225c7ba6e645a89ff17e101aede6625b3 (diff) | |
| download | upstream-30e47fb1e4f128e76b10fa3e0ff55c0497a9096a.tar.gz upstream-30e47fb1e4f128e76b10fa3e0ff55c0497a9096a.tar.bz2 upstream-30e47fb1e4f128e76b10fa3e0ff55c0497a9096a.zip | |
ramips: mt7620: ethernet: use more macros and bump version
Define and use some missing macros,
and use them instead of BIT() or numbers for more readable code.
Add comment for a bit change that seems unrelated to ethernet
but is actually needed (PCIe Root Complex mode).
Remove unknown and unused macro RST_CTRL_MCM
(probably from MT7621 / MT7622)
This is the last of a series of fixes, so bump version.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 88a0cebadfecb6ebb9f5f535e74f7f7574f513f3)
Diffstat (limited to 'target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c index ae90f0484d..7c91e5840b 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c @@ -65,9 +65,11 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw) { u32 i; u32 val; - u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1; + u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1; + + /* Internal ethernet requires PCIe RC mode */ + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1); - rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR); /* Enable MIB stats */ @@ -83,7 +85,7 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw) mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) | (gsw->ephy_base << 16), GSW_REG_GPC1); - fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */ + fe_reset(MT7620A_RESET_EPHY); pr_info("gsw: ephy base address: %d\n", gsw->ephy_base); } |