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author | Gabor Juhos <juhosg@openwrt.org> | 2012-09-12 19:03:12 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-09-12 19:03:12 +0000 |
commit | 0a42b02126bf220768fcece1ab9e82e302005808 (patch) | |
tree | 854ea30ba5816b91c81b9261535f5f0f0aa58f9b /target/linux/ramips/files/arch/mips/ralink/rt305x | |
parent | 6804bafaddec8f36c7c8fd7b0a5469d35cf8bc7f (diff) | |
download | upstream-0a42b02126bf220768fcece1ab9e82e302005808.tar.gz upstream-0a42b02126bf220768fcece1ab9e82e302005808.tar.bz2 upstream-0a42b02126bf220768fcece1ab9e82e302005808.zip |
ramips/rt305x: add initial support for Rt5350 SoC
Somehow detecting the RAM size in common/setup.c doesn't
work here, it always detects 64M and then crashes on devices
with less RAM.
Probably using MEMC_REG_SDRAM_CFG1 to know the RAM size is how
it could be, for now I use the mem=32M kernel parameter to get
stuff working.
Signed-off-by: Daniel Golle <dgolle@allnet.de>
SVN-Revision: 33381
Diffstat (limited to 'target/linux/ramips/files/arch/mips/ralink/rt305x')
3 files changed, 26 insertions, 2 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c index 958547611b..c46a1747b5 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c @@ -62,6 +62,27 @@ void __init rt305x_clocks_init(void) rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; rt305x_uart_clk.rate = 40000000; rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else if (soc_is_rt5350()) { + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & + RT5350_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT5350_SYSCFG0_CPUCLK_360: + rt305x_cpu_clk.rate = 360000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + break; + case RT5350_SYSCFG0_CPUCLK_320: + rt305x_cpu_clk.rate = 320000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4; + break; + case RT5350_SYSCFG0_CPUCLK_300: + rt305x_cpu_clk.rate = 300000000; + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + break; + default: + BUG(); + } + rt305x_uart_clk.rate = 40000000; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; } else { BUG(); } diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c index 07e950ad9b..92ae56d3be 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/devices.c @@ -404,7 +404,7 @@ void __init rt305x_register_usb(void) { if (soc_is_rt305x() || soc_is_rt3350()) { platform_device_register(&rt305x_dwc_otg_device); - } else if (soc_is_rt3352()) { + } else if (soc_is_rt3352() || soc_is_rt5350()) { platform_device_register(&rt3352_ehci_device); platform_device_register(&rt3352_ohci_device); } else { diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c index 179f9b7bc4..856d869ebe 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c @@ -54,6 +54,9 @@ void __init ramips_soc_prom_init(void) } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { rt305x_soc = RT305X_SOC_RT3352; name = "RT3352"; + } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { + rt305x_soc = RT305X_SOC_RT5350; + name = "RT5350"; } else { panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); } @@ -68,7 +71,7 @@ void __init ramips_soc_prom_init(void) ramips_mem_base = RT305X_SDRAM_BASE; - if (soc_is_rt305x() || soc_is_rt3350()) { + if (soc_is_rt305x() || soc_is_rt3350() || soc_is_rt5350()) { ramips_mem_size_min = RT305X_MEM_SIZE_MIN; ramips_mem_size_max = RT305X_MEM_SIZE_MAX; } else if (soc_is_rt3352()) { |