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author | Gabor Juhos <juhosg@openwrt.org> | 2011-01-26 20:48:50 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2011-01-26 20:48:50 +0000 |
commit | 7c1dfa170622f032cf37055b4c36409e806613df (patch) | |
tree | ffba635c0890f282d041dd9d8875adc454637bc4 /target/linux/ramips/files/arch/mips/include | |
parent | 777c494bef8c0673cae9c1404c87ba1594b00381 (diff) | |
download | upstream-7c1dfa170622f032cf37055b4c36409e806613df.tar.gz upstream-7c1dfa170622f032cf37055b4c36409e806613df.tar.bz2 upstream-7c1dfa170622f032cf37055b4c36409e806613df.zip |
ramips: add watchdog device for RT288x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25129 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include')
-rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h index 1dd6c2dcec..a95cb82963 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h @@ -33,6 +33,7 @@ #define RT2880_SDRAM_BASE 0x08000000 #define RT2880_SYSC_SIZE 0x100 +#define RT2880_TIMER_SIZE 0x100 #define RT2880_INTC_SIZE 0x100 #define RT2880_MEMC_SIZE 0x100 #define RT2880_UART0_SIZE 0x100 @@ -45,6 +46,7 @@ #define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */ #define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */ #define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ +#define SYSC_REG_CLKCFG 0x030 #define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ #define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ #define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ @@ -62,6 +64,8 @@ #define SYSTEM_CONFIG_CPUCLK_280 0x2 #define SYSTEM_CONFIG_CPUCLK_300 0x3 +#define CLKCFG_SRAM_CS_N_WDT BIT(9) + #define RT2880_RESET_SYSTEM BIT(0) #define RT2880_RESET_TIMER BIT(1) #define RT2880_RESET_INTC BIT(2) |