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| author | Gabor Juhos <juhosg@openwrt.org> | 2009-09-04 15:08:26 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2009-09-04 15:08:26 +0000 |
| commit | 8d8a4e727481a58495f8c3b9dfd2e92650d85e10 (patch) | |
| tree | 08dcd82358322b24a2b85a010a18144d7721ac83 /target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | |
| parent | 8691bbb699556ab797d74d635cc360732d9b92de (diff) | |
| download | upstream-8d8a4e727481a58495f8c3b9dfd2e92650d85e10.tar.gz upstream-8d8a4e727481a58495f8c3b9dfd2e92650d85e10.tar.bz2 upstream-8d8a4e727481a58495f8c3b9dfd2e92650d85e10.zip | |
add GPIO configuration feature
SVN-Revision: 17512
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h')
| -rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index d4a1920633..7f0666d5b1 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -49,6 +49,7 @@ #define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ #define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ #define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ +#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ #define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ #define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ @@ -61,6 +62,25 @@ #define SYSTEM_CONFIG_CPUCLK_320 0x0 #define SYSTEM_CONFIG_CPUCLK_384 0x1 +#define RT305X_GPIO_MODE_I2C BIT(0) +#define RT305X_GPIO_MODE_SPI BIT(1) +#define RT305X_GPIO_MODE_UART0_SHIFT 2 +#define RT305X_GPIO_MODE_UART0_MASK 0x7 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) +#define RT305X_GPIO_MODE_UARTF 0x0 +#define RT305X_GPIO_MODE_PCM_UARTF 0x1 +#define RT305X_GPIO_MODE_PCM_I2S 0x2 +#define RT305X_GPIO_MODE_I2S_UARTF 0x3 +#define RT305X_GPIO_MODE_PCM_GPIO 0x4 +#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 +#define RT305X_GPIO_MODE_GPIO_I2S 0x6 +#define RT305X_GPIO_MODE_GPIO 0x7 +#define RT305X_GPIO_MODE_UART1 BIT(5) +#define RT305X_GPIO_MODE_JTAG BIT(6) +#define RT305X_GPIO_MODE_MDIO BIT(7) +#define RT305X_GPIO_MODE_SDRAM BIT(8) +#define RT305X_GPIO_MODE_RGMII BIT(9) + #define RT305X_RESET_SYSTEM BIT(0) #define RT305X_RESET_TIMER BIT(8) #define RT305X_RESET_INTC BIT(9) |