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| author | Rosen Penev <rosenp@gmail.com> | 2018-06-07 10:36:19 -0700 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-06-08 09:31:36 +0200 |
| commit | 66cc6dd6c4b19a8ef9e5d2ebed3e10876c8aeaf0 (patch) | |
| tree | f9ec28810466896fdf9e84114f0d501620e68c39 /target/linux/ramips/files-4.14 | |
| parent | 8110bf18f4c1d04e8dfe94438caeadf78ceac892 (diff) | |
| download | upstream-66cc6dd6c4b19a8ef9e5d2ebed3e10876c8aeaf0.tar.gz upstream-66cc6dd6c4b19a8ef9e5d2ebed3e10876c8aeaf0.tar.bz2 upstream-66cc6dd6c4b19a8ef9e5d2ebed3e10876c8aeaf0.zip | |
ramips: mmc: Add back some non-mt7621 code that staging removed
This reverts commit 8a570921b5ba49a2d3824f1220e4c53809063468.
This seems to have been accidentally reverted. This fixes mt7620 and
mt7628.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/ramips/files-4.14')
| -rw-r--r-- | target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c index 2a032fcba1..97ae927d2d 100644 --- a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c +++ b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c @@ -2209,7 +2209,23 @@ static int msdc_drv_probe(struct platform_device *pdev) // Set the pins for sdxc to sdxc mode //FIXME: this should be done by pinctl and not by the sd driver - reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18); + if (ralink_soc == MT762X_SOC_MT7620A || + ralink_soc == MT762X_SOC_MT7621AT) { + reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + + 0x60)) & ~(0x3 << 18); + if (ralink_soc == MT762X_SOC_MT7620A) + reg |= 0x1 << 18; + } else { + reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c)); + reg |= 0x1e << 16; + sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c), reg); + reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + + 0x60)) & ~(0x3 << 10); +#if defined(CONFIG_MTK_MMC_EMMC_8BIT) + reg |= 0x3 << 26 | 0x3 << 28 | 0x3 << 30; +#endif + } + sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x60), reg); hw = &msdc0_hw; |