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authorLoveSy <shana@zju.edu.cn>2018-05-28 09:46:28 +0800
committerJohn Crispin <john@phrozen.org>2018-07-30 10:43:37 +0200
commit3a8efaef00d6b7317c46fe6b7e923912d8bf3500 (patch)
tree8ac874a59a299d3f9954d0c7c211e811d2cf6340 /target/linux/ramips/files-4.14/drivers/mmc
parentb4d4e4ceb56825033dd4c8e401e9250ae5042a99 (diff)
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ramips: mmc: Fix init for MT7628AN
There is another thing about crc to do when initialize SD card on MT7628. This commit is to fix this init issue. Signed-off-by: LoveSy <shana@zju.edu.cn>
Diffstat (limited to 'target/linux/ramips/files-4.14/drivers/mmc')
-rw-r--r--target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h1
-rw-r--r--target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c16
2 files changed, 16 insertions, 1 deletions
diff --git a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h
index 33fa59a019..a3c50d0528 100644
--- a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h
+++ b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h
@@ -234,6 +234,7 @@ enum {
#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
+#define MSDC_IOCON_WDSPL (0x1 << 8) /* RW */
#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
diff --git a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c
index 97ae927d2d..e1493290a0 100644
--- a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c
+++ b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c
@@ -1796,6 +1796,9 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
MSDC_SMPL_FALLING);
sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,
MSDC_SMPL_FALLING);
+ /* sdxc: set sample crc by clock falling edge. Added by zhangzf */
+ if (ralink_soc == MT762X_SOC_MT7628AN)
+ sdr_set_field(MSDC_IOCON, MSDC_IOCON_WDSPL, MSDC_SMPL_FALLING);
//} /* for tuning debug */
} else { /* default value */
sdr_write32(MSDC_IOCON, 0x00000000);
@@ -2205,7 +2208,7 @@ static int msdc_drv_probe(struct platform_device *pdev)
struct msdc_host *host;
struct msdc_hw *hw;
int ret;
- u32 reg;
+ u32 reg, reg1;
// Set the pins for sdxc to sdxc mode
//FIXME: this should be done by pinctl and not by the sd driver
@@ -2215,6 +2218,17 @@ static int msdc_drv_probe(struct platform_device *pdev)
0x60)) & ~(0x3 << 18);
if (ralink_soc == MT762X_SOC_MT7620A)
reg |= 0x1 << 18;
+ }
+ else if (ralink_soc == MT762X_SOC_MT7628AN) {
+ /* Fixed MT7628 SDXC init by zhangzf */
+ reg &= ~((0x3 << 0)|(0x3 << 6)|(0x3 << 10)|(0x1 << 15)|(0x3 << 20)|(0x3 << 24));
+ reg |= ((0x1 << 0)|(0x1 << 6)|(0x1 << 10)|(0x1 << 15)|(0x1 << 20)|(0x1 << 24));
+#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
+ reg |= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
+#endif
+ reg1 = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x1340));
+ reg1 |= (0x1 << 11); //Normal mode(AP mode), SDXC CLK=PAD_GPIO0=GPIO11, driving = 8mA
+ sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x1340), reg1);
} else {
reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c));
reg |= 0x1e << 16;