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author | John Crispin <john@openwrt.org> | 2013-04-03 09:58:44 +0000 |
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committer | John Crispin <john@openwrt.org> | 2013-04-03 09:58:44 +0000 |
commit | d4db00205d726f9faca3147cb345518ec5406aab (patch) | |
tree | 2e4466b8176c978c765dfeac1ea5f6ab5a0a203a /target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c | |
parent | 86a691144b4988d2ebfb78834b608dec51b53a33 (diff) | |
download | upstream-d4db00205d726f9faca3147cb345518ec5406aab.tar.gz upstream-d4db00205d726f9faca3147cb345518ec5406aab.tar.bz2 upstream-d4db00205d726f9faca3147cb345518ec5406aab.zip |
move files to files-3.7
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 36161
Diffstat (limited to 'target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c')
-rw-r--r-- | target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c new file mode 100644 index 0000000000..5a069db454 --- /dev/null +++ b/target/linux/ramips/files-3.7/arch/mips/ralink/rt305x/setup.c @@ -0,0 +1,88 @@ +/* + * Ralink RT305x SoC specific setup + * + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> + * + * Parts of this file are based on Ralink's 2.6.21 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/clk.h> + +#include <asm/mips_machine.h> +#include <asm/reboot.h> +#include <asm/time.h> + +#include <asm/mach-ralink/common.h> +#include <asm/mach-ralink/rt305x.h> +#include <asm/mach-ralink/rt305x_regs.h> +#include "common.h" + +static void rt305x_restart(char *command) +{ + rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL); + while (1) + if (cpu_wait) + cpu_wait(); +} + +static void rt305x_halt(void) +{ + while (1) + if (cpu_wait) + cpu_wait(); +} + +unsigned int __cpuinit get_c0_compare_irq(void) +{ + return CP0_LEGACY_COMPARE_IRQ; +} + +void __init ramips_soc_setup(void) +{ + struct clk *clk; + + rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE); + rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE); + + rt305x_clocks_init(); + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type, + clk_get_rate(clk) / 1000000, + (clk_get_rate(clk) % 1000000) * 100 / 1000000); + + _machine_restart = rt305x_restart; + _machine_halt = rt305x_halt; + pm_power_off = rt305x_halt; + + clk = clk_get(NULL, "uart"); + if (IS_ERR(clk)) + panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); + + ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk), + RT305X_INTC_IRQ_UART0); + ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk), + RT305X_INTC_IRQ_UART1); +} + +void __init plat_time_init(void) +{ + struct clk *clk; + + clk = clk_get(NULL, "cpu"); + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + mips_hpt_frequency = clk_get_rate(clk) / 2; +} |