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| author | Weijie Gao <hackpascal@gmail.com> | 2018-11-19 00:07:01 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-11-26 12:13:52 +0100 |
| commit | ed25e3ac02d9193d7cba89563a88b8bccc4b4513 (patch) | |
| tree | 7a4fe550187ca65f416d9cfb1398e3e849c3d840 /target/linux/ramips/dts | |
| parent | c7ca224299e77f5d822dd154b99fe9aeefc550be (diff) | |
| download | upstream-ed25e3ac02d9193d7cba89563a88b8bccc4b4513.tar.gz upstream-ed25e3ac02d9193d7cba89563a88b8bccc4b4513.tar.bz2 upstream-ed25e3ac02d9193d7cba89563a88b8bccc4b4513.zip | |
ramips: fix some clocks in mt7621.dtsi
As the cpu clock calculation has been fixed, the clock for gic and spi
should be also fixed.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Diffstat (limited to 'target/linux/ramips/dts')
| -rw-r--r-- | target/linux/ramips/dts/mt7621.dtsi | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 89f3f6fe2d..3c610e49d5 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -41,14 +41,6 @@ clock-output-names = "cpu", "bus"; }; - cpuclock: cpuclock { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - sysclock: sysclock { #clock-cells = <0>; compatible = "fixed-clock"; @@ -176,7 +168,6 @@ compatible = "ns16550a"; reg = <0xc00 0x100>; - clocks = <&sysclock>; clock-frequency = <50000000>; interrupt-parent = <&gic>; @@ -193,7 +184,7 @@ compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&pll MT7621_CLK_BUS>; resets = <&rstctrl 18>; reset-names = "spi"; @@ -402,7 +393,7 @@ timer { compatible = "mti,gic-timer"; interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; - clocks = <&cpuclock>; + clocks = <&pll MT7621_CLK_CPU>; }; }; |