ramips: add support for D-Link DWR-960

The DWR-960 Wireless Router is based on the MT7620A SoC.

Specification:

- MediaTek MT7620A (580 Mhz)
- 128 MB of RAM
- 16 MB of FLASH
- 1x 802.11bgn radio
- 1x 802.11ac radio (MT7610 mpcie card)
- 4x 10/100 Mbps Ethernet (1 WAN and 3 LAN)
- 1x 10/100/1000 Mbps Ethernet (1 LAN) (AR8035)
- 2x internal, non-detachable antennas (Wifi 2.4G)
- 3x external, detachable antennas (2x LTE, 1x Wifi 5G)
- 1x LTE modem
- UART (J4) header on PCB (57600 8n1)
- 9x LED, 2x button
- JBOOT bootloader

Known issues:
- Flash is extremely slow.

Installation:
Apply factory image via http web-gui or JBOOT recovery page

How to revert to OEM firmware:
- push the reset button and turn on the power. Wait until LED start
  blinking (~10sec.)
- upload original factory image via JBOOT http (IP: 192.168.123.254)

Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>

1 files changed, 190 insertions, 0 deletions

diff --git a/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts b/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts
new file mode 100644
index 0000000000..063d65a70d
--- /dev/null
+++ b/target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "mt7620a.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "dlink,dwr-960", "ralink,mt7620a-soc";
+	model = "D-Link DWR-960";
+
+	aliases {
+		led-boot = &led_status;
+		led-failsafe = &led_status;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: status {
+			label = "dwr-960:green:status";
+			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+		};
+
+		wan {
+			label = "dwr-960:green:wan";
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+		};
+
+		lan {
+			label = "dwr-960:green:lan";
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+		};
+
+		sms {
+			label = "dwr-960:green:sms";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+
+		signal_green {
+			label = "dwr-960:green:signal";
+			gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		signal_red {
+			label = "dwr-960:red:signal";
+			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		4g {
+			label = "dwr-960:green:4g";
+			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+		};
+
+		3g {
+			label = "dwr-960:green:3g";
+			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+		};
+
+		wlan5g {
+			label = "dwr-960:green:wlan5g";
+			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		wlan2g {
+			label = "dwr-960:green:wlan2g";
+			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+	};
+};
+
+&ethernet {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii2_pins &mdio_pins>;
+	mediatek,portmap = "wllll";
+
+	port@5 {
+		status = "okay";
+		phy-mode = "rgmii-txid";
+		phy-handle = <&phy7>;
+	};
+
+	mdio-bus {
+		status = "okay";
+
+		phy7: ethernet-phy@7 {
+			reg = <7>;
+			phy-mode = "rgmii-id";
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "jboot";
+				reg = <0x0 0x10000>;
+				read-only;
+			};
+
+			partition@10000 {
+				compatible = "amit,jimage";
+				label = "firmware";
+				reg = <0x10000 0xfe0000>;
+			};
+
+			config: partition@ff0000 {
+				label = "config";
+				reg = <0xff0000 0x10000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		ieee80211-freq-limit = <5000000 6000000>;
+		mediatek,mtd-eeprom = <&config 0xe08e>;
+		mtd-mac-address = <&config 0xe50e>;
+		mtd-mac-address-increment = <2>;
+	};
+};
+
+&state_default {
+	default {
+		ralink,group = "i2c", "wled", "spi refclk", "uartf", "ephy";
+		ralink,function = "gpio";
+	};
+};