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authorMichael Pratt <mcpratt@pm.me>2021-04-03 14:42:51 -0400
committerPetr Štetiar <ynezz@true.cz>2022-04-19 14:48:21 +0200
commit687646587581962572b5b0b805d2088feae36ec8 (patch)
tree65b6fef716c8bbc8c42672926edc33b13d4758c3 /target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
parent5d7805c78b7d8e9f02e53fdb2237971fa3353296 (diff)
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ramips: mt7620: use DTS to set PHY base address for external PHYs
Set the PHY base address to 12 for mt7530 and 8 for others, which is based on the default setting for some devices from printing the register with the following command after it is written to by uboot during the boot cycle. `md 0x10117014 1` PHY_BASE option only uses 5 bits of the register, bits 16 to 20, so use 8-bit integer type. Set the option using the DTS property mediatek,ephy-base and create the gsw node if missing. Also, added a kernel message to display the EPHY base address. Note: If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf) then there is adverse effects with Atheros switches. Signed-off-by: Michael Pratt <mcpratt@pm.me> (cherry picked from commit 0976b6c4262a11a8d0dab9aeb64f5cdee266c44a)
Diffstat (limited to 'target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts')
-rw-r--r--target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts b/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
index 962ef3371d..ee845c7b5e 100644
--- a/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
+++ b/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
@@ -150,6 +150,10 @@
};
};
+&gsw {
+ mediatek,ephy-base = /bits/ 8 <8>;
+};
+
&pcie {
status = "okay";
};