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author | John Crispin <john@openwrt.org> | 2013-04-03 09:59:46 +0000 |
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committer | John Crispin <john@openwrt.org> | 2013-04-03 09:59:46 +0000 |
commit | 770b28f146f7bf9495013a57504258d7f92263c4 (patch) | |
tree | 108bd1da2423d8916f6ad235490bc3397faccd3d /target/linux/ramips/dts/mt7620.dtsi | |
parent | 2328e8389e20c0a4c5d3ed2a98019d29da5dd4b4 (diff) | |
download | upstream-770b28f146f7bf9495013a57504258d7f92263c4.tar.gz upstream-770b28f146f7bf9495013a57504258d7f92263c4.tar.bz2 upstream-770b28f146f7bf9495013a57504258d7f92263c4.zip |
add the dts files that describe the boards in future
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 36168
Diffstat (limited to 'target/linux/ramips/dts/mt7620.dtsi')
-rw-r--r-- | target/linux/ramips/dts/mt7620.dtsi | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7620.dtsi b/target/linux/ramips/dts/mt7620.dtsi new file mode 100644 index 0000000000..c0eb5bce80 --- /dev/null +++ b/target/linux/ramips/dts/mt7620.dtsi @@ -0,0 +1,136 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc"; + + cpus { + cpu@0 { + compatible = "mips,mips24KEc"; + }; + }; + + chosen { + bootargs = "console=ttyS0,57600 init=/init"; + }; + + cpuintc: cpuintc@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + palmbus@10000000 { + compatible = "palmbus"; + reg = <0x10000000 0x200000>; + ranges = <0x0 0x10000000 0x1FFFFF>; + + #address-cells = <1>; + #size-cells = <1>; + + sysc@0 { + compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc"; + reg = <0x0 0x100>; + }; + + timer@100 { + compatible = "ralink,mt7620-timer", "ralink,rt2880-timer"; + reg = <0x100 0x20>; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + + watchdog@120 { + compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt"; + reg = <0x120 0x10>; + }; + + intc: intc@200 { + compatible = "ralink,mt7620-intc", "ralink,rt2880-intc"; + reg = <0x200 0x100>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + memc@300 { + compatible = "ralink,mt7620-memc", "ralink,rt3050-memc"; + reg = <0x300 0x100>; + }; + + gpio0: gpio@600 { + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio"; + reg = <0x600 0x34>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,num-gpios = <24>; + ralink,register-map = [ 00 04 08 0c + 20 24 28 2c + 30 34 ]; + }; + + gpio1: gpio@638 { + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio"; + reg = <0x638 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,num-gpios = <16>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + }; + + gpio2: gpio@660 { + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio"; + reg = <0x660 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,num-gpios = <32>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + }; + + gpio3: gpio@688 { + compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio"; + reg = <0x688 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,num-gpios = <1>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + }; + + spi@b00 { + compatible = "ralink,rt3883-spi", "ralink,rt2880-spi"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uartlite@c00 { + compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + + interrupt-parent = <&intc>; + interrupts = <12>; + + reg-shift = <2>; + }; + }; +}; |